dropout voltage, and high output voltage accuracy,
make it ideal for battery applications. EN input
connected to CMOS has low bias current. The
space-saving SOT23-5L and TSOT23-5L package
is attractive for “Pocket” and “Hand Held”
applications.
This rugged device has both thermal shutdown, and
current limit protections to prevent device failure
under the “Worst” operating conditions.
In a low noise, regulated supply application, a 10nF
capacitor is necessary to be placed in between
Bypass and Ground.
The AP139 is stable with a low ESR output
capacitor of 1.0µF or greater.
Applications
- Battery-powered devices
- Personal communication devices
- Home electric/electronic appliances
- PC peripherals
Pin Assignments
(Top View)
Pin Descriptions
4
V
OUT
5
BYP
AP139
Pin
Name
V
IN
GND
EN
BYP
V
OUT
Pin
No.
1
2
3
4
5
Function
Power Supply
Ground
Enable Pin
Bypass Signal Pin
Output
1
2
3
V
IN
GND EN
SOT23-5/TSOT23-5
Ordering Information
AP139 XX X X
Output voltage
15: 1.5V
18: 1.8V
20: 2.0V
25: 2.5V
28: 2.8V
30: 3.0V
33: 3.3V
35: 3.5V
Package
W : SOT23-5L
TW:TSOT23-5L
Packing
Blank: Tube
A: Taping
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 1.0 Nov 08, 2005
1/8
AP139
300mA Low-Noise CMOS LDO
Block Diagram
V
IN
V
OUT
Current
Limit
1uA
Thermal
Shutdown
R1
EN
BYP
-
AMP
+
Vref
R2
GND
Absolute Maximum Ratings
Symbol
V
IN
I
OUT
V
OUT
T
A
T
J
Parameter
Input Voltage
Output Current
Output Voltage
ESD Classification
Ambient Temperature Range
Junction Temperature Range
Rating
+7
P
D
/ (V
IN
-V
O
)
GND - 0.3 to V
IN
+ 0.3
B
-40 to +85
-40 to +125
Unit
V
mA
V
ºC
ºC
Thermal Information
Symbol
θjc
P
D
T
J
T
Lead
Parameter
Thermal Resistance
Internal Power Dissipation (∆T=100 ºC)
Maximum Junction Temperature
Maximum Lead Temperature (10 sec)
SOT23-5L
SOT23-5L
Maximum
160
250
150
300
Unit
ºC/W
mW
ºC
ºC
Anachip Corp.
www.anachip.com.tw
2/8
Rev. 1.0 Nov 08, 2005
AP139
300mA Low-Noise CMOS LDO
Electrical Characteristics
(T
A
=+25ºC, unless otherwise noted.)
Symbol
Parameter
V
IN
Input Voltage
I
Q
Quiescent Current
I
STB
Standby Current
V
OUT
V
OUT
Temperature
Coefficient
Test Conditions
I
O
=0mA
V
IN
=5.0V, V
OUT
=0V, V
EN
< V
EL
Min.
Note 1
-
-
-2
-
Typ.
-
45
2.0
-
50
-
-
-
-
-
-
450
150
0.1
0.3
60
50
40
75
55
30
-
-
-
130
20
Max.
7
60
3.0
2
-
1.5
1.2
1
0.6
0.45
-
-
300
0.3
1
-
-
-
-
-
-
-
0.8
<0.1
-
-
Unit
V
µA
µA
%
ppm/
o
C
Output Voltage Accuracy I
O
=1mA, V
IN
=5V
V
DROPOUT
Dropout Voltage
I
O
=1mA to 300mA,
V
OUT
=V
O(NOM)
-1.5%
V
O
=1.5V
V
O
=1.8V
V
O
=2V
V
O
=2.5V
V
O
≥2.8V
I
OUT
I
LIMIT
Output Current
Current Limit
V
OUT
> 1.05V
Vcc=5V,Vout<1.05V
I
OUT
=5mA, V
IN
=5~7V
I
O
=1mA to 300mA, V
IN
=5V
f=1KHz
I
O
=100mA,
Power Supply Rejection
f=10KHz
C
O
=2.2µF ceramic
f=100KHz
f=1KHz
I
O
=100mA,
Power Supply Rejection C
O
=2.2µF ceramic,
f=10KHz
C
BYP
=20nF
f=100KHz
Output ON
EN Input Threshold
Output OFF
Enable Pin Current
Over Temperature
Shutdown
Over Temperature
Hysteresis
-
-
-
-
-
300
300
-
-
-
-
-
-
-
-
-
1.7
-
-
-
-
V
mA
mA
mA
%
%
dB
dB
V
V
µA
o
o
I
short
Short Circuit Current
△V
LINE
Line Regulation
△V
LOAD
Load Regulation
PSRR
PSRR
V
EH
V
EL
I
EN
OTS
OTH
C
C
Note 1. : V
IN(MIN)
=V
OUT
+V
DROPOUT
Typical Application
IN
V
IN
AP139
BYP
C1
1uF
C2
10nF
GND
EN
C3
1uF
V
OUT
OUT
Anachip Corp.
www.anachip.com.tw
3/8
Rev. 1.0
Nov 08, 2005
AP139
300mA Low-Noise CMOS LDO
Typical Performance Characteristics
100
90
Vcc Vs Quiescent Current
1.6
1.4
Vout Vs Dropout Voltage
Quiescent Current (μA)
80
60
50
40
30
20
10
0
3.5
4
4.5
5
5.5
6
TA=25℃
Dropout Voltage (V)
70
1.2
1
0.8
0.6
0.4
0.2
Io=300mA
Io=200mA
Io=100mA
1.5
1.8
2
2.5
Vout (V)
2.8
3
3.3
3.5
6.5
7
0
Vcc (V)
0
-10
-20
-30
Power Supply Rejection Ratio
Iout=100mA
0
-10
-20
-30
BP=10nF
Power Supply Rejection Ratio
100mA
PSRR (dB)
PSRR (dB)
-40
-50
BP=1nF
-60
-70
-80
-90
1.0E+00
BP=20nF
1.0E+01
1.0E+02
1.0E+03
1.0E+04
1.0E+05 1.0E+06
BP=5nF
-40
10mA
-50
-60
1mA
-70
BP=10nF
-80
-90
1.0E+00
1.0E+05 1.0E+06
1.0E+01
1.0E+02
1.0E+03
1.0E+04
Frequency (Hz)
Frequency (Hz)
Power Supply Rejection Ratio
0
BP=0
-10
-20
-30
100mA
Vout Vs Current Limit
0.7
0.6
0.5
Current Limit (A)
PSRR (dB)
-40
-50
-60
10mA
0.4
0.3
0.2
0.1
Vcc=5V
0
1mA
-70
-80
-90
1.0E+00
1.0E+01
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.5
1.8
2
2.5
2.8
3
3.3
3.5
Frequency (Hz)
Vout (V)
Anachip Corp.
www.anachip.com.tw
4/8
Rev. 1.0
Nov 08, 2005
AP139
300mA Low-Noise CMOS LDO
Typical Performance Characteristics (Continued)
Vcc Vs Short Current
400
350
300
Short Current (mA)
250
200
150
100
50
0
3.5
Top to bottom
Vout=1.5V
Vout=1.8V
Vout=2.5V
Vout=3.3V
4
4.5
5
5.5
6
6.5
7
Vcc (V)
Function Description
The AP139 of CMOS regulators contain a PMOS
pass transistor, voltage reference, error amplifier,
over-current protection, thermal shutdown.
The P-channel pass transistor receives data from
the error amplifier, over-current protection, and
thermal protection circuits. During normal operation,
the error amplifier compares the output voltage to a
precision reference. Over-current and thermal
shutdown circuits become active when the junction
temperature exceeds 130
o
C, or the current exceeds
300mA. During thermal shutdown, the output
voltage remains low. Normal operation is restored
when the junction temperature drops below 110
o
C.
The AP139 switches from voltage mode to current
mode when the load exceeds the rated output
current. This prevents over-stress.
Enable
The enable pin normally floats high. When actively,
pulled low, the PMOS pass transistor shut off, and
all internal circuits are powered down. In this state,
the quiescent current is less than 2µA. This pin
behaves much like an electronic switch.
External Capacitor
The AP139 is stable with a low ESR output
capacitor to ground of 1.0µF or greater. It can keep
stable even with higher ESR capacitors. A second
capacitor is recommended between the input and
ground to stabilize VIN. The input capacitor should
be larger than 0.1µF to have a beneficial effect. All
capacitors should be placed in close proximity to
the pins. A “quiet” ground termination is desirable.
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