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CJ53FM-FREQ-OUT23

Description
CMOS/TTL Output Clock Oscillator, 1.8MHz Min, 100MHz Max,
CategoryPassive components    oscillator   
File Size135KB,1 Pages
ManufacturerCal Crystal Lab Inc / Comclok Inc
Websitehttps://www.transko.com
Download Datasheet Parametric View All

CJ53FM-FREQ-OUT23 Overview

CMOS/TTL Output Clock Oscillator, 1.8MHz Min, 100MHz Max,

CJ53FM-FREQ-OUT23 Parametric

Parameter NameAttribute value
MakerCal Crystal Lab Inc / Comclok Inc
Reach Compliance Codecompliant
maximum descent time5 ns
Frequency Adjustment - MechanicalNO
frequency stability15%
JESD-609 codee4
Installation featuresSURFACE MOUNT
Maximum operating frequency100 MHz
Minimum operating frequency1.8 MHz
Maximum operating temperature70 °C
Minimum operating temperature-10 °C
Oscillator typeCMOS/TTL
Output load10 TTL, 15 pF
physical size7.5mm x 5mm x 1.6mm
longest rise time5 ns
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry47.5/52.5 %
Terminal surfaceGOLD
Cal Crystal Lab, Inc. / Comclok, Inc. 800-333-9825
1156 North Gilbert Street • Anaheim, CA 92801
CERAMIC SURFACE MOUNT OSCILLATORS
MODEL
MODEL
Model
Frequency Range
Frequency Stability
Operating Temperature Range
Storage Temperature Range
Current Consumption
Supply Voltage
Symmetry
Rise & Fall Time (Tr, Tf)
Logic “1”
Logic “0”
Output Load
Aging
Stand-by Current “0” Lev. at #1
Enable Condition (optional)
Reflow Condition
DIMENSIONS
(mm)
Inches
CJ 3.3V SMD
CH 5.0V SMD
CH
CJ
1.8000MHz ~ 100.000MHz
100ppm Standard, Optional Tolerances Available
-10
o
C ~ +70
o
C
-55
o
C ~ +125
o
C
1.8MHz to 36.0MHz : 15mA
36.0MHz to 70.0MHz : 25mA
70.0MHz to 100.0MHz : 40mA
1.8000MHz ~ 100.000MHz
100ppm Standard, Optional Tolerances Available
-10
o
C ~ +70
o
C
-55
o
C ~ +125
o
C
1.8MHz to 32.0MHz : 10mA
32.0MHz to 50.0MHz : 18mA
50.0MHz to 70.0MHz : 20mA
+ 3.3VDC
±
10%
60/40 @ 50% Vcc HCMOS or TTL 1.4V
Optional Tolerances Available
+ 5.0VDC
±
10%
60/40 @ 50% Vcc HCMOS or TTL 1.4V
Optional Tolerances Available
5ns Max
2.97VDC Min
0.33VDC Max
1 to 10 TTL / 15pF
< 5ppm per year
10µA Max
Enable - Logic “1” 2.0VDC Min
Disable - Logic “0” 0.5VDC Max
10ns Max
4.5VDC Min
0.5VDC Max
1 to 10 TTL / 15pF
< 5ppm per year
NA
Enable - Logic “1” 2.0VDC Min
Disable - Logic “0” 0.5VDC Max
o
o
+240 C
±
5 C for 10 seconds
o
o
+150 C
±
10 C for 1 to 2 minutes (preheating)
CASE DIMENSIONS
OSC With Tri-State
PIN
CONNECTION
#1
“L”
“H” or Open
#2
GND
Z
Output
#3
#4
Vcc
Z: high impedance
RECOMMENDED LAND PATTERN
OSC Without Tri-State
PIN
CONNECTION
#1
N.C.
#2
GND
#3
OUTPUT
#4
VDD
OUTPUT WAVEFORM
PACKAGE DATA
Item
Package
Lid
Base
Sealing
Terminal Plating
Metal
Ceramic
Seam-weld
Gold
TEST CIRCUIT
C
L
: including fixture and probe capacitance
TAPE SPECIFICATIONS
1,000 PCS. PER REEL (180MM DIA.)
34
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