CL10K50SQC240-2 datasheet, PDF

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CL10K50SQC240-2: DescriptionField Programmable Gate Array; CategoryProgrammable logic devices Programmable logic; File Size192KB，18 Pages; ManufacturerClear Logic

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CL10K50SQC240-2 Overview

Field Programmable Gate Array

CL10K50SQC240-2 Parametric

Parameter Name	Attribute value
Maker	Clear Logic
package instruction	,
Reach Compliance Code	unknown

CL10K50SQC240-2 Preview

Key Features

CL10K50S

Fully Compatible to the Altera

FLEX

10KS Family

Prototype Your System With Altera FPGAs

Seamlessly Migrate Production To Clear Logic

No ASIC Engineering, No NRE, And No Test Vector

Development

Very Fast, Dense Signal Routing Using Vertical Link

Interconnect

"Gate Array" Option Eliminates Configuration EPROMs

LIBERATOR

Parameter

Typical Gates

(Logic and RAM)

Maximum System Gates

Logic Elements

Embedded Array Blocks

Total RAM Bits

Max User I/O pins

Speed Grades

CL10K30E

30,000

119,000

1,728

24,576

220

-1, -2, -3

144-pin TQFP

208-pin PQFP

256-pin FBGA

484-pin FBGA

Fabricated Using 0.25 Micron CMOS Process

Very Low Power Consumption (Active And Standby)

High Density

- 50,000 Usable Gates

- 2,880 Logic Elements

- 40,960 RAM Bits

- 254 Maximum User I/O Pins

CL10K50E

CL10K50S

50,000

199,000

2,880

40,960

254

-1, -2, -3

144-pin TQFP

208-pin PQFP

240-pin PQFP

256-pin FBGA

356-pin SBGA

484-pin FBGA

CL10KE Product Family Overview

CL10K100E

100,000

257,000

4,992

49,152

338

-1, -2, -3

208-pin PQFP

240-pin PQFP

256-pin FBGA

356-pin SBGA

484-pin FBGA

CL10K200E

CL10K200S

200,000

513,000

9,984

98,304

470

-1, -2, -3

240-pin PQFP

356-pin SBGA

484-pin FBGA

600-pin SBGA

672-pin FBGA

10KE tbl 01

Packages

June 2001

Page 1

LIBERATOR CL10K50S (PRELIMINARY)

Description

The LIBERATOR

CL10KS family offers you all of the time-to-

market benefits of designing with programmable logic. Simply

use Altera FLEX 10KS FPGAs to prototype and verify the design.

Then, take five minutes to submit the bitstream using Clear

Logic's web site! Within eight weeks, your system can be in

volume production using compatible Clear Logic devices.

LIBERATOR technology frees you to completely design,

prototype, and verify your custom logic using Altera FLEX 10KS

products. Clear Logic's innovative technology eliminates NRE

costs, test vector development, ordering minimums, and long lead

times. No re-simulation or re-layout is required, because Clear

Logic offers an architecture that is exactly compatible to the

functionality of the FPGA prototype. Clear Logic's NoFault

test

technology ensures complete test coverage through the use of

special scan test registers.

The LIBERATOR family is based upon an array of logic

elements. Each logic element contains a configurable look-up

table for combinatorial functions and a register for sequential

operations. Eight logic elements in a group form a block. Logic

functions and signal routing are defined by Clear Logic's

proprietary vertical metal links.

Laser-based configuration allows quick-turn prototyping and

eliminates NRE costs for photomasks. Inherent CL10KS family

performance benefits include extremely consistent propagation

delays, reduced power consumption, and improved immunity to

noise and upset events.

Configuration

The "Gate Array" configuration mode eliminates the need for

external EPROMs or software configuration. The LIBERATOR

device is already factory-configured when it is shipped. When

using the device in the "Gate Array" mode, it powers up fully

configured. In this mode, if the customer selects INIT_DONE

option, this pin will always be high.

Page 2

LIBERATOR CL10K50S (PRELIMINARY)

Additional

Information

For further information on designing with the LIBERATOR

family, please refer to these documents:

AN-01: Requesting a First Article. This document provides

instructions on how to request first articles by submitting a

bitstream file to Clear Logic's web site.

AN-02: Clear Logic Packaging Guide. This document provides

specifications and drawings for packages used by the CL10K

family and other Clear Logic devices.

AN-13: LIBERATOR -- A New Way To Design. This document

describes the most efficient path for custom logic designs up

to 200K gates using FPGA design techniques and going to

production with Clear Logic.

AN-14: CL10K Technology White Paper. This document

outlines the technologies employed by the LIBERATOR

family.

AN-15: LIBERATOR System Configuration. This document

contains a detailed discussion of all aspects of configuring

CL10K-based systems.

AN-16: Introduction to the Clear Logic Verilog Model

Generator. Clear Logic now has Verilog models of your FPGA

converted design. Learn what it is and how it can help you.

AN-17: Clear Logic LIBERATOR Design Models. This

document outlines the capabilities and freedom available in

the Clear Logic Verilog and VHDL design models.

AN-18: Debugging Designs Using Clear Logic Models. This

document shows the enhanced troubleshooting capabilities

that the Clear Logic LIBERATOR Verilog/VHDL design

models bring to the system debugging process.

Page 3

LIBERATOR CL10K50S (PRELIMINARY)

Block Diagram

Embedded Array Block (EAB)

I/O Element

(IOE)

IOE IOE

IOE

Column

Interconnect

EAB

IOE

Logic Array

Logic Building

Block (LBB)

IOE

Logic Element (LE)

IOE

Row

Interconnect

Logic

Array

EAB

Local Interconnect

10KE drw 01

IOE IOE

IOE

IOE IOE

Logical Memory Array (LMA)

Page 4

LIBERATOR CL10K50S (PRELIMINARY)

Pin Configuration

Pin Name

MSEL0

MSEL1

nSTATUS

nCONFIG

DCLK

CONF_DONE

INIT_DONE

nCE

nCEO

nWS

nRS

nCS

RDYnBSY

CLKUSR

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

144-Pin TQFP

107

106

142

141

144

143

116

114

113

112

111

110

109

108

208-Pin PQFP

108

107

105

155

154

206

204

208

207

166

164

162

161

159

158

157

156

240-Pin PQFP

124

123

121

179

178

238

236

240

239

190

188

186

185

183

182

181

180

10K50S tbl 01A

Page 5

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CL10K50SQC240-2 Related Products

	CL10K50SQC240-2	CL10K50STC144-2X	CL10K50STC144-2	CL10K50SFC256-2X	CL10K50SFC256-3	CL10K50SQC208-1	CL10K50SQC208-2	CL10K50SQC240-3	CL10K50SQI208-2	CL10K50STC144-1
Description	Field Programmable Gate Array	Field Programmable Gate Array	Field Programmable Gate Array	Field Programmable Gate Array	Field Programmable Gate Array	Field Programmable Gate Array	Field Programmable Gate Array	Field Programmable Gate Array	Field Programmable Gate Array	Field Programmable Gate Array
Maker	Clear Logic	Clear Logic	Clear Logic	Clear Logic	Clear Logic	Clear Logic	Clear Logic	Clear Logic	Clear Logic	Clear Logic
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown

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