time is measured from the latter of device enable, output
enable, or valid address to valid data output.
SRAM Read Cycle 1, the Address Access in Figure 3a, is
initiated by a change in address inputs while the chip is
enabled with G asserted and W deasserted. Valid data appears
on data outputs DQ(31:0) after the specified t
AVQV
is
satisfied. Outputs remain active throughout the entire cycle.
As long as device enable and output enable are active, the
address inputs may change at a rate equal to the minimum
read cycle time (t
AVAV
).
SRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 3b, is initiated by the latter of either E1and E2 going
active while G remains asserted, W remains deasserted, and
the addresses remain stable for the entire cycle. After the
specified t
ETQV
is satisfied, the 32-bit word addressed by
A(18:0) is accessed and appears at the data outputs DQ(31:0).
SRAM Read Cycle 3, the Output Enable-controlled Access
in Figure 3c, is initiated by G going active while E1 and E2
are asserted, W is deasserted, and the addresses are stable.
Read access time is t
GLQV
unless t
AVQV
or t
ETQV
(reference
Figure 3b) have not been satisfied.
SRAM EDAC Status Indications during a Read Cycle, if
MBE is Low, the data is good. If MBE is High the data is
corrupted.
WRITE CYCLE
is initiated by either E1or E2 going active. For the W initiated
write, unless the outputs have been previously placed in the
high-impedance state by G, the user must wait t
WLQZ
before
applying data to the thirty-two bidirectional pins DQ(31:0)
to avoid bus contention.
MEMORY SCRUBBING/CYCLE STEALING
The UT8ER512K32 SRAM uses architectural improvements
and embedded error detection and correction to maintain
unsurpassed levels of SEU protection. This is accomplished
by what Aeroflex refers to as Cycle Stealing. When the device
asserts BUSY_WARNING followed by BUSY, the user must
de-assert E1 or E2 within the minimum specification for an
access cycle (t
AVAV
). To minimize the system design impact
for reduced speed operation, the edge relationship between
BUSY_WARNING and BUSY is programmable via the
sequence described in figure 5a.
The effective error rate will be flux dependent (rate at which
radiation is applied) and not simply LET dependent. As a
result, some users may desire an increased scrub rate to lower
the error rate at the sacrifice of reduced total throughput,
while others may desire a lower scrub rate to increase the total
throughput and accept a higher error rate in a low flux
environment. This rate at which the SRAM controller will
correct errors from the memory is user programmable. The
required sequence is described in figure 5a.
EV
A combination of W and E1 less than V
IL
(max) and E2
greater than V
IH
(min) defines a write cycle. The state of G is
a “don’t care” for a write cycle. The outputs are placed in the
high-impedance state when either G is greater than V
IH
(min),
or when W is less than V
IL
(max).
Write Cycle 1, the Write Enable-controlled Access in Figure
4a, is defined by a write terminated by W going high, with
E1 and E2 still active. The write pulse width is defined by
t
WLWH
when the write is initiated by W, and by t
ETWH
when
the write is initiated by E1 and E2. Unless the outputs have
been previously placed in the high-impedance state by G, the
t
WLQZ
before applying data to the 32 bidirectional pins
DQ(31:0) to avoid bus contention.
EL
O
3
PM
Total Dose
Heavy Ion
Error Rate
2
Data is corrected not only during the internal scrub, but again
during a user requested read cycle. If the MBE signal is
asserted once the data is valid (t
AVAV
), if the data presented
contains at least two errors and should be considered corrupt.
RADIATION HARDNESS
The UT8ER512K32 SRAM incorporates special design,
layout, and process features which allows operation in a
limited radiation environment.
Table 3. Radiation Hardness Design Specifications
1
100K
TBD
rad(Si)
Errors/Bit-Day
IN
D
Notes:
1. The SRAM is immune to latchup to particles >100MeV-cm
2
/mg.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
SUPPLY SEQUENCING
No supply voltage sequencing is required between V
DD1
and
V
DD2
.
Write Cycle 2, the Chip Enable-controlled Access in Figure
4b, is defined by a write terminated by the latter of E1 or E2
going inactive. The write pulse width is defined by t
WLEF
when the write is initiated by W, and by t
ETEF
when the write
EN
T
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD1
V
DD2
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
Thermal resistance, junction-to-case
2
DC input current
LIMITS
-0.3 to 2.0V
-0.3 to 3.8V
-0.3 to 3.8V
-65 to +150°C
1.2W
+150°C
5°C/W
±
5 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Test per MIL-STD-883, Method 1012.
SYMBOL
V
DD1
V
DD2
T
C
V
IN
PARAMETER
Positive supply voltage
Positive supply voltage
Case temperature range
DC input voltage
PM
4
O
IN
D
EV
EL
EN
RECOMMENDED OPERATING CONDITIONS
(C) Screening: -55 to +125°C
(W) Screening: -40 to +125°C
0V to V
DD2
T
LIMITS
1.7 to 1.9V
3.0 to 3.6V
DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*
(-55°C to +125°C for (C) screening and -40°C to +125°C for (W) screening)
SYMBOL
V
IH
V
IL
V
OL
V
OH
C
IN1
C
IO1
I
IN
I
OZ
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
Input leakage current
Three-state output leakage current
I
OL
= 8mA,V
DD2
=V
DD2
(min)
I
OH
= -4mA,V
DD2
=V
DD2
(min)
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
V
IN
= V
DD2
and V
SS
V
O
= V
DD2
and V
SS
V
DD2
= V
DD2
(max), G = V
DD2
(max)
V
DD2
= V
DD2
(max), V
O
= V
DD2
V
DD2
= V
DD2
(max), V
O
= V
SS
Inputs : V
IL
= V
SS
+ 0.2V,
-2
-2
.8*V
DD2
12
12
2
2
CONDITION
MIN
.7*V
DD2
.3*V
DD2
.2*V
DD2
MAX
UNIT
V
V
V
V
pF
pF
µA
µA
I
OS2, 3
Short-circuit output current
-100
+100
mA
T
EN
I
DD1
(OP
1
)
V
DD1
Supply current operating
@ 1MHz
25
mA
V
IH
= V
DD2
-0.2V, I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
I
DD2
(OP
2
)
EL
O
I
DD2
(OP
1
)
PM
I
DD1
(OP
2
)
V
DD1
Supply current operating
@ 50MHz,
Inputs : V
IL
= V
SS
+ 0.2V,
V
IH
= V
DD2
-0.2V, I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
Inputs : V
IL
= V
SS
+ 0.2V,
V
IH
= V
DD2
-0.2V, I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
Inputs : V
IL
= V
SS
+ 0.2V,
V
IH
= V
DD2
-0.2V, I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
CMOS inputs , I
OUT
= 0
E1 = V
DD2
-0.2, E2 = GND
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
200
mA
V
DD2
Supply current operating
@ 1MHz
1
mA
V
DD2
Supply current operating
@ 50MHz,
12
mA
EV
I
DD1
(SB)
4
I
DD2
(SB)
4
I
DD1
(SB)
4
I
DD2
(SB)
4
Supply current standby @ 0Hz
25
100
25
100
mA
µA
mA
µA
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 3.0E5 rad(Si).
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
京公网安备 11010802033920号
EEWORLD
