DS1230Y/AB
DS1230Y/AB
256K Nonvolatile SRAM
FEATURES
PIN ASSIGNMENT
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
•
10 years minimum data retention in the absence of
external power
•
Data is automatically protected during power loss
•
DIP-package devices directly replace 32K x 8 volatile
static RAM or EEPROM
•
Unlimited write cycles
•
Low-power CMOS
•
Read and write access times as fast as 70 ns
•
Lithium energy source is electrically disconnected to
retain freshness until power is applied for the first time
•
Full
±10%
V
CC
operating range (DS1230Y)
•
Optional
±5%
V
CC
operating range (DS1230AB)
•
Optional
industrial temperature range of
+85
o
C, designated IND
-40
o
C
to
GND
•
JEDEC standard 28-pin DIP package
•
Low Profile Module (LPM) package
– Fits into standard 68-pin PLCC surface-mount-
able sockets
– 250 mil package height
28-PIN ENCAPSULATED PACKAGE
740 MIL EXTENDED
PIN DESCRIPTION
A0 - A14
DQ0 - DQ7
CE
WE
OE
V
CC
GND
-
-
-
-
-
-
-
Address Inputs
Data In/Data Out
Chip Enable
Write Enable
Output Enable
Power (+5V)
Ground
NC
NC
NC
NC
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34–PIN LOW PROFILE MODULE (LPM)
ECopyright
1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
100395 1/10
DS1230Y/AB
DESCRIPTION
The DS1230 256K Nonvolatile SRAMs are 262,144-bit,
fully static, nonvolatile SRAMs organized as 32,768
words by 8 bits. Each NV SRAM has a self-contained
lithium energy source and control circuitry which con-
stantly monitors V
CC
for an out-of-tolerance condition.
When such a condition occurs, the lithium energy
source is automatically switched on and write protection
is unconditionally enabled to prevent data corruption.
DIP-package DS1230 devices can be used in place of
existing 32K x 8 static RAMs directly conforming to the
popular bytewide 28-pin DIP standard. The DIP devices
also match the pinout of 28256 EEPROMs, allowing di-
rect substitution while enhancing performance.
DS1230 devices in the Low Profile Module package are
specifically designed for surface-mount applications.
There is no limit on the number of write cycles that can
be executed and no additional support circuitry is re-
quired for microprocessor interfacing.
WE will determine the start of the write cycle. The write
cycle is terminated by the earlier rising edge of CE or
WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (t
WR
) before another cycle can
be initiated. The OE control signal should be kept inac-
tive (high) during write cycles to avoid bus contention.
However, if the output drivers are enabled (CE and OE
active) then WE will disable the outputs in t
ODW
from its
falling edge.
DATA RETENTION MODE
The DS1230AB provides full functional capability for
V
CC
greater than 4.75 volts and write protects by 4.5
volts. The DS1230Y provides full functional capability
for V
CC
greater than 4.5 volts and write protects by 4.25
volts. Data is maintained in the absence of V
CC
without
any additional support circuitry. The nonvolatile static
RAMs constantly monitor V
CC
. Should the supply volt-
age decay, the NV SRAMs automatically write protect
themselves, all inputs become “don’t care,” and all out-
puts become high impedance. As V
CC
falls below ap-
proximately 3.0 volts, a power switching circuit con-
nects the lithium energy source to RAM to retain data.
During power-up, when V
CC
rises above approximately
3.0 volts, the power switching circuit connects external
V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds
4.75 volts for the DS1230AB and 4.5 volts for the
DS1230Y.
READ MODE
The DS1230 devices execute a read cycle whenever
WE (Write Enable) is inactive (high) and CE (Chip En-
able) and OE (Output Enable) are active (low). The
unique address specified by the 15 address inputs (A
0
-
A
14
) defines which of the 32,768 bytes of data is to be
accessed. Valid data will be available to the eight data
output drivers within t
ACC
(Access Time) after the last
address input signal is stable, providing that CE and OE
(Output Enable) access times are also satisfied. If OE
and CE access times are not satisfied, then data access
must be measured from the later occurring signal (CE or
OE) and the limiting parameter is either t
CO
for CE or t
OE
for OE rather than address access.
FRESHNESS SEAL
Each DS1230 device is shipped from Dallas Semicon-
ductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first
applied at a level greater than 4.25 volts, the lithium en-
ergy source is enabled for battery back-up operation.
WRITE MODE
The DS1230 devices execute a write cycle whenever
the WE and CE signals are active (low) after address in-
puts are stable. The later occurring falling edge of CE or
100395 2/10
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