ESMT
DDR II SDRAM
M14D128168A (2M)
2M x 16 Bit x 4 Banks
DDR II SDRAM
Features
JEDEC Standard
V
DD
= 1.8V ± 0.1V, V
DDQ
= 1.8V ± 0.1V
Internal pipelined double-data-rate architecture; two data access per clock cycle
Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
1KB page size
-
-
Row address: A0 to A11
Column address: A0 to A8
Quad bank operation
CAS Latency : 3, 4, 5, 6, 7
Additive Latency: 0, 1, 2, 3, 4, 5
Burst Type : Sequential and Interleave
Burst Length : 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for READ; center-aligned with data for WRITE
Data mask (DM) for write masking only
On-Die-Termination for better signal quality
Special function support
-
-
-
50/ 75/ 150 ohm ODT
High Temperature Self refresh rate enable
DCC (Duty Cycle Corrector)
Auto & Self refresh
Refresh cycle :
-
-
4096 cycles/64ms (15.6μs refresh interval) at 0
℃ ≦
T
C
≦ +85 ℃
4096 cycles/32ms (7.8μs refresh interval) at
+85 ℃ ＜
T
C
≦
+95
℃
SSTL_18 interface
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
1/59
ESMT
Ordering Information:
Product ID
M14D128168A - 1.8BG2M
M14D128168A - 2.5BG2M
M14D128168A - 1.8BVG2M
M14D128168A - 2.5BVG2M
M14D128168A - 1.8BBG2M
M14D128168A - 2.5BBG2M
M14D128168A - 1.8BBVG2M
M14D128168A - 2.5BBVG2M
Max Freq.
533MHz
400MHz
533MHz
400MHz
533MHz
400MHz
533MHz
400MHz
V
DD
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
Data Rate
(CL-tRCD-tRP)
DDR2-1066 (7-7-7)
DDR2-800 (5-5-5)
DDR2-1066 (7-7-7)
DDR2-800 (5-5-5)
DDR2-1066 (7-7-7)
DDR2-800 (5-5-5)
DDR2-1066 (7-7-7)
DDR2-800 (5-5-5)
M14D128168A (2M)
Package
84 ball FBGA
(Window BGA)
A (max) = 1.2mm
84 ball VFBGA
A (max) = 1.2mm
Comments
Pb-free
84 ball FBGA
(Window BGA)
A (max) = 1.0mm
84 ball VFBGA
A (max) = 1.0mm
Functional Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
2/59
ESMT
Ball Configuration (Top View)
M14D128168A (2M)
(FBGA / VFBGA 84, 8mmX12.5mmX1.2mm Body, 0.8mm Ball Pitch)
(FBGA / VFBGA 84, 8mmX12.5mmX1.0mm Body, 0.8mm Ball Pitch)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
V
DD
V
SS
NC
V
DD
DQ14
2
NC
V
SSQ
DQ9
V
SSQ
NC
V
SSQ
DQ1
V
SSQ
V
REF
CKE
BA0
A10
A3
A7
A12
3
V
SS
UDM
V
DDQ
7
V
SSQ
8
UDQS
9
V
DDQ
DQ15
V
DDQ
DQ13
V
DDQ
UDQS
V
SSQ
V
DDQ
DQ12
V
DD
DQ6
V
DDQ
DQ4
V
DDL
V
DDQ
DQ10
V
SSQ
DQ8
V
SSQ
LDQS
DQ11
V
SS
LDM
LDQS
V
DDQ
V
SSQ
DQ0
V
SSQ
CLK
CLK
CS
A0
A4
A8
NC
DQ7
V
DDQ
DQ5
V
DD
ODT
V
DDQ
DQ3
V
SS
DQ2
V
SSDL
RAS
CAS
A2
A6
A11
NC
WE
BA1
A1
A5
A9
NC
V
DD
V
SS
Note: A12 (ball R2) is used for MRS/EMRS.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
3/59
ESMT
Ball Description
Pin Name
Function
Address inputs
- Row address A0~A11
- Column address A0~A8
A12: use for MRS/EMRS
A10/AP : Auto Precharge
BA0, BA1 : Bank selects (4 Banks)
Data-in/Data-out
Command input
Command input
Command input
Ground
Power
Bi-directional differential Data Strobe.
LDQS and /LDQS are DQS for DQ0~DQ7;
UDQS and /UDQS are DQS for DQ8~DQ15.
On-Die-Termination.
ODT is only applied to DQ0~DQ15, DM, DQS
and /DQS.
No connection
Pin Name
M14D128168A (2M)
Function
A0~A12,
BA0,BA1
DM
(LDM, UDM)
DM is an input mask signal for write data.
LDM is DM for DQ0~DQ7 and UDM is DM
for DQ8~DQ15.
DQ0~DQ15
RAS
CAS
WE
CLK, CLK
CKE
CS
V
DDQ
V
SSQ
V
REF
Differential clock input
Clock enable
Chip select
Supply Voltage for DQ
Ground for DQ
Reference Voltage
V
SS
V
DD
DQS, DQS
(LDQS, LDQS
UDQS, UDQS )
ODT
NC
V
DDL
Supply Voltage for DLL
V
SSDL
Ground for DLL
Absolute Maximum Rating
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Voltage on V
DDL
supply relative to V
SS
Voltage on V
DDQ
supply relative to V
SS
Storage temperature
Symbol
V
IN
, V
OUT
V
DD
V
DDL
V
DDQ
T
STG
Value
-0.5 ~ 2.3
-1.0 ~ 2.3
-0.5 ~ 2.3
-0.5 ~ 2.3
-55 ~ +100
Unit
V
V
V
V
°C (
Note *)
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
Note *:
Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
4/59
ESMT
Operation Temperature Condition
Parameter
Operation temperature
Symbol
T
C
M14D128168A (2M)
Value
0 ~ +95
Unit
°C
Note: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM.
2. Supporting 0 to +85℃ with full AC and DC specifications.
Supporting 0 to + 85℃ and being able to extend to + 95
℃
with doubling auto-refresh commands in frequency to a
32ms period ( t
REFI
= 7.9μs ) and higher temperature Self-Refresh entry via A7 “1” on EMRS(2).
DC Operation Condition & Specifications
DC Operation Condition
(Recommended DC operating conditions)
Parameter
Supply voltage
Supply voltage for DLL
Supply voltage for output
Input reference voltage
Termination voltage (system)
Input logic high voltage
Input logic low voltage
(All voltages referenced to VSS)
Parameter
Output minimum source DC current ( V
DDQ
(min); V
OUT
=1.42V )
Output minimum sink DC current ( V
DDQ
(min); V
OUT
=
0.28V )
Note:
1. The value of V
REF
may be selected by the user to provide optimum noise margin in the system. Typically the value of
V
REF
is expected to be about 0.5 x V
DDQ
of the transmitting device and V
REF
is expected to track variations in V
DDQ
.
2. Peak to peak AC noise on V
REF
may not exceed
±2%
V
REF
(DC).
3. V
TT
of transmitting device must track V
REF
of receiving device.
4. V
DDQ
and V
DDL
track V
DD
. AC parameters are measured with V
DD
, V
DDQ
and V
DDL
tied together.
5. The DC value of V
REF
applied to the receiving device is expected to be set to V
TT
.
6. T
C
= 25℃, V
DD
= V
DDQ
= 1.8V.
7. There is no specific device V
DD
supply voltage requirement for SSTL_18 compliance. However, under all conditions
V
DDQ
must be less than or equal to V
DD
.
Symbol
I
OH
I
OL
Value
-13.4
+13.4
Unit
mA
mA
Note
5,6
5,6
Symbol
V
DD
V
DDL
V
DDQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
Min.
1.7
1.7
1.7
0.49 x V
DDQ
V
REF
- 0.04
V
REF
+ 0.125
-0.3
Typ.
1.8
1.8
1.8
0.5 x V
DDQ
V
REF
-
-
Max.
1.9
1.9
1.9
0.51 x V
DDQ
V
REF
+ 0.04
V
DDQ
+ 0.3
V
REF
- 0.125
Unit
V
V
V
V
V
V
V
Note
4,7
4,7
4,7
1,2,7
3,7
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
5/59
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