ST7PLITEU09U0U3 datasheet, PDF

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ST7PLITEU09U0U3: DescriptionMICROCONTROLLER, DSO8, ROHS COMPLIANT, DFN-8; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，139 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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ST7PLITEU09U0U3 Overview

MICROCONTROLLER, DSO8, ROHS COMPLIANT, DFN-8

ST7PLITEU09U0U3 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	DFN
package instruction	ROHS COMPLIANT, DFN-8
Contacts	8
Reach Compliance Code	compliant
Has ADC	YES
Address bus width
bit size	8
CPU series	ST72
maximum clock frequency	8 MHz
DMA channel	NO
External data bus width
JESD-30 code	R-XDSO-N8
length	3.5 mm
Number of I/O lines	6
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	UNSPECIFIED
encapsulated code	SON
Encapsulate equivalent code	SOLCC8,.12,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3/5 V
Certification status	Not Qualified
RAM (bytes)	128
rom(word)	2048
ROM programmability	MROM
speed	8 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	3.3 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	NO LEAD
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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ST7LITEU05

ST7LITEU09

8-bit MCU with single voltage Flash memory,

ADC, timers

Features

■

Memories

– 2K Bytes single voltage Flash program

memory with readout protection, in-circuit

and in-application programming (ICP and

IAP). 10K write/erase cycles guaranteed,

data retention: 20 years at 55 °C

– 128 bytes RAM

– 128 bytes data EEPROM. 300K write/erase

cycles guaranteed, data retention: 20 years

at 55 °C

■

Clock, reset and supply management

– 3-level low voltage supervisor (LVD) and

auxiliary voltage detector (AVD) for safe

power- on/off procedures

– Clock sources: internal trimmable 8-MHz

RC oscillator, internal low power, low

frequency RC oscillator or external clock

– Five Power Saving Modes: Halt, Auto-

Wakeup from Halt, Active-halt, Wait and

Slow

■

Interrupt management

– 11 interrupt vectors plus TRAP and RESET

– 5 external interrupt lines (on 5 vectors)

■

I/O Ports

– 5 multifunctional bidirectional I/O lines

– 1 additional output line

– 6 alternate function lines

Table 1.

Device summary

Features

ST7LITEU05

Program memory - bytes

RAM (stack) - bytes

EEPROM -bytes

Peripherals

Operating supply

CPU frequency

Operating temperature

Packages

DIP8

DFN8

SO8

150”

■

– 5 high sink outputs

2 timers

– One 8-bit lite timer (LT) with prescaler

including: watchdog, 1 realtime base and 1

input capture

– One 12-bit auto-reload timer (AT) with

output compare function and PWM

A/D converter

– 10-bit resolution for 0 to V

– 5 input channels

Instruction set

– 8-bit data manipulation

– 63 basic instructions with illegal opcode

detection

– 17 main addressing modes

– 8 x 8 unsigned multiply instruction

Development tools

– Full hardware/software development

package

– Debug module

ST7ULTRALITE

ST7LITEU09

128 (64)

128

LT timer w/ Wdg, AT timer w/ 1 PWM, 10-bit ADC

2.4 V to 3.3 V @f

CPU

= 4 MHz, 3.3 V to 5.5 V @f

CPU

= 8 MHz

up to 8 MHz RC

-40 °C to +125 °C

SO8 150”, DIP8, DFN8, DIP16

(1)

1. For development or tool prototyping purposes only. Not orderable in production quantities.

October 2008

Rev 2

1/139

www.st.com

Contents

ST7LITEU05 ST7LITEU09

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1

4.2

4.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.3.1

4.3.2

In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

In Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.4

4.5

ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5.1

4.5.2

Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.6

4.7

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.7.1

Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1

5.2

5.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3.1

5.3.2

Read operation (E2LAT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Write operation (E2LAT=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.4.1

5.4.2

5.4.3

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.5

5.6

5.7

Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/139

ST7LITEU05 ST7LITEU09

5.7.1

Contents

EEPROM control/status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . 26

Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1

6.2

6.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.1

7.2

7.3

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

Main clock control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . 35

RC control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 36

AVD threshold selection register (AVDTHCR) . . . . . . . . . . . . . . . . . . . . 36

Clock controller control/status register (CKCNTCSR) . . . . . . . . . . . . . . 37

7.4

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.4.1

7.4.2

7.4.3

7.4.4

7.4.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 39

Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.5

7.5.1

7.5.2

Multiplexed IO reset control register 1 (MUXCR1) . . . . . . . . . . . . . . . . . 41

Multiplexed IO reset control register 0 (MUXCR0) . . . . . . . . . . . . . . . . . 41

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Priority management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Interrupts and low power mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.1

8.2

Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3/139

Contents

ST7LITEU05 ST7LITEU09

8.3

Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.3.1

8.3.2

External interrupt control register 1 (EICR1) . . . . . . . . . . . . . . . . . . . . . 45

External interrupt control register 2 (EICR2) . . . . . . . . . . . . . . . . . . . . . 45

8.4

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.4.1

8.4.2

8.4.3

8.4.4

Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.1

9.2

9.3

9.4

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Active-halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.4.1

9.4.2

Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.5

Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.5.1

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.1

10.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.2.1

10.2.2

10.2.3

10.2.4

Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.3

10.4

10.5

10.6

Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

11.1

Lite timer (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

11.1.1

11.1.2

11.1.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4/139

ST7LITEU05 ST7LITEU09

11.1.4

11.1.5

11.1.6

11.1.7

Contents

Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

11.2

12-bit autoreload timer (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.3

10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

11.3.1

11.3.2

11.3.3

11.3.4

11.3.5

11.3.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

12.1

ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

12.1.1

12.1.2

12.1.3

12.1.4

12.1.5

12.1.6

12.1.7

Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Indexed mode (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

12.2

Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

12.2.1

Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

13.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

13.1.1

13.1.2

13.1.3

13.1.4

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

5/139

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Hardware Engineer's Manual (Huawei Internal Reference): Hardware Engineer's Manual (Huawei Internal Reference)...; 程序天使 DSP and ARM Processors

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RSL10 problem SWD idcod cannot be obtained solution and small pit sharing: The moment I got the board, I first thought it was small and suitable for embedding. I spent a while looking for the programming port, but later I found it in the schematic diagram and chose to jumper...; lehuijie onsemi and Avnet IoT Innovation Design Competition

Simple and easy automatic charging

Emergency hand-held lamps powered by 6V maintenance-free batteries are widely used in rural areas. The charger used is a transformer step-down and single diode half-wave rectifier, and the charging...[Details]
Analysis of the significance of using M430/OS on the MSP430 MCU

introduction 1 The significance of using RTOS on MSP430 It is understandable that it is meaningless to use RTOS on MSP430. Because the hardware resources of MSP430 are limited (for exampl...[Details]
Dynamic power management based on Linux: making embedded devices more energy-efficient

To differentiate their products in a crowded and competitive market, manufacturers of handheld devices often consider battery life and power management as key selling points for cell phones, PDAs, ...[Details]
Altera Launches Latest IP Core Products

July 11, 2012, Beijing - Altera Corporation (NASDAQ: ALTR) today announced the launch of 40-Gbps Ethernet (40GbE) and 100-Gbps Ethernet (100GbE) intellectual property (IP) core products. These core...[Details]
Application example of CIF50-PB bus card and force control configuration software

1. Introduction to CIF Board Fieldbus integration based on PC system Whether it is a master or a slave, fieldbus has won unanimous praise in the field of PC-based automation. For more...[Details]
Experiment of using 51 single chip microcomputer to drive buzzer to sound

In the single-chip microcomputer system, in addition to display devices, sound devices are often used, and the most common sound device is the buzzer. Buzzers are generally used for some low-demand...[Details]
LED Floodlights and Floodlights

1 What is an LED floodlight? LED downlights are also called spotlights, projection lamps, and spotlights. They are mainly used for architectural decorative lighting and commercial space lighti...[Details]
Application of portable power supply

Portable power applications are broad and varied. Products range from wireless sensor nodes with average power consumption of only a few microwatts to in-vehicle medical or data acquisition systems...[Details]
Battery maintenance precautions

a. Keep the battery clean, wipe off the spilled electrolyte, contaminated dirt and dust in time; keep the poles and terminal clamps clean and in good contact, and apply vaseline or butter to preven...[Details]
Application of ASI fieldbus in spent anode washing and stacking unit

1. Introduction AS-Interface bus technology is an intelligent network that uses a single cable to connect sensors and actuators to controllers, transmit data, and provide power. It can be used...[Details]
Current detection in vehicle systems

Current sensing in automotive applications includes controlling the current through solenoids and injectors. For example, during diesel injection, we rapidly increase the current to the induction i...[Details]
Research on Memory Detection System Based on LabVIEW

During the operation of electronic equipment, memory failure or failure will not only lead to economic losses, but also may lead to catastrophic consequences. Therefore, memory testing has ...[Details]
Using timer interrupts to prevent interference

After the development of the single-chip microcomputer application system is completed, the system often freezes at the work site due to noise interference, electromagnetic interference, overvoltag...[Details]
Cost Control in the Design Stage of Electronic Products

In the process of designing electronic products, we usually control the cost of the designed products, always try to simplify the circuit, reduce the components, and simplify the installation process....[Details]
Design of interface circuit between DSP and AD converter

Abstract: In a digital signal processing system with DSP as the core, analog-to-digital conversion is an important part of the system. Taking TMS320C6203B and ADS5422 of Texas Instruments ...[Details]

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