BV80605001908AK/SLBJJ datasheet, PDF

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BV80605001908AK/SLBJJ: DescriptionRISC Microprocessor, 64-Bit, 2800MHz, CMOS, PBGA1156,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size475KB，94 Pages; ManufacturerIntel; Websitehttp://www.intel.com/; Environmental Compliance

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BV80605001908AK/SLBJJ Overview

RISC Microprocessor, 64-Bit, 2800MHz, CMOS, PBGA1156,

BV80605001908AK/SLBJJ Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Intel
package instruction	LGA, LGA1156,40X40,36
Reach Compliance Code	compliant
bit size	64
JESD-30 code	S-PBGA-N1156
Number of terminals	1156
Package body material	PLASTIC/EPOXY
encapsulated code	LGA
Encapsulate equivalent code	LGA1156,40X40,36
Package shape	SQUARE
Package form	GRID ARRAY
power supply	0.65/1.4 V
Certification status	Not Qualified
speed	2800 MHz
Maximum slew rate	110000 mA
surface mount	YES
technology	CMOS
Terminal form	NO LEAD
Terminal pitch	0.9 mm
Terminal location	BOTTOM
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Intel

Core™ i7-800 and i5-700

Desktop Processor Series

Datasheet – Volume 1

This is volume 1 of 2

July 2010

Document Number: 322164-004

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING

TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE

FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.



Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different

processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in

clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular

feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/

processor_number for details.

Intel

Active Management Technology requires the computer system to have an Intel(R) AMT-enabled chipset, network hardware and software, as well

as connection with a power source and a corporate network connection. Setup requires configuration by the purchaser and may require scripting with

the management console or further integration into existing security frameworks to enable certain functionality. It may also require modifications of

implementation of new business processes. With regard to notebooks, Intel AMT may not be available or certain capabilities may be limited over a host

OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see www.intel.com/

technology/platform-technology/intel-amt/

Intel® Trusted Execution Technology (Intel® TXT) requires a computer system with Intel® Virtualization Technology (Intel® Virtualization Technology

(Intel® VT-x) and Intel® Virtualization Technology for Directed I/O (Intel® VT-d)), a Intel TXT-enabled processor, chipset, BIOS, Authenticated Code

Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an

application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some

uses. For more information, see http://www.intel.com/technology/security

Intel

Virtualization Technology requires a computer system with an enabled Intel

processor, BIOS, virtual machine monitor (VMM) and, for some uses,

certain computer system software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software

configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your

application vendor.

Warning: Altering clock frequency and/or voltage may (i) reduce system stability and useful life of the system and processor; (ii) cause the processor

and other system components to fail; (iii) cause reductions in system performance; (iv) cause additional heat or other damage; and (v) affect system

data integrity. Intel has not tested, and does not warranty, the operation of the processor beyond its specifications.

* Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance

varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo

Boost Technology. For more information, see http://www.intel.com/technology/turboboost

Hyper-threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology-enabled chipset, BIOS, and

operating system. Performance will vary depending on the specific hardware and software you use. For more information including details on which

processors support HT Technology, see http://www.intel.com/info/hyperthreading.

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications

enabled for Intel

64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for

more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check

with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

Enhanced Intel SpeedStep

Technology for specified units of this processor available Q2/06. See the Processor Spec Finder at http://

processorfinder.intel.com or contact your Intel representative for more information.

Intel, Intel Core, Core Inside, Intel Speedstep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others.

Datasheet, Volume 1

Contents

Introduction

.............................................................................................................. 9

1.1

Processor Feature Details ................................................................................... 11

1.1.1 Supported Technologies .......................................................................... 11

1.2

Interfaces ........................................................................................................ 11

1.2.1 System Memory Support ......................................................................... 11

1.2.2 PCI Express* ......................................................................................... 12

1.2.3 Direct Media Interface (DMI).................................................................... 13

1.2.4 Platform Environment Control Interface (PECI) ........................................... 13

1.3

Power Management Support ............................................................................... 14

1.3.1 Processor Core....................................................................................... 14

1.3.2 System ................................................................................................. 14

1.3.3 Memory Controller.................................................................................. 14

1.3.4 PCI Express* ......................................................................................... 14

1.4

Thermal Management Support ............................................................................ 14

1.5

Package ........................................................................................................... 14

1.6

Terminology ..................................................................................................... 15

1.7

Related Documents ........................................................................................... 17

Interfaces................................................................................................................

2.1

System Memory Interface .................................................................................. 19

2.1.1 System Memory Technology Supported ..................................................... 19

2.1.2 System Memory Timing Support............................................................... 20

2.1.3 System Memory Organization Modes......................................................... 20

2.1.3.1 Single-Channel Mode................................................................. 20

2.1.3.2 Dual-Channel Mode—Intel

Flex Memory Technology Mode ............ 21

2.1.4 Rules for Populating Memory Slots ............................................................ 22

2.1.5 Technology Enhancements of Intel

Fast Memory Access (Intel

FMA).......... 23

2.1.5.1 Just-in-Time Command Scheduling.............................................. 23

2.1.5.2 Command Overlap .................................................................... 23

2.1.5.3 Out-of-Order Scheduling ............................................................ 23

2.1.6 System Memory Pre-Charge Power Down Support Details ............................ 23

2.2

PCI Express* Interface....................................................................................... 24

2.2.1 PCI Express* Architecture ....................................................................... 24

2.2.1.1 Transaction Layer ..................................................................... 25

2.2.1.2 Data Link Layer ........................................................................ 25

2.2.1.3 Physical Layer .......................................................................... 25

2.2.2 PCI Express* Configuration Mechanism ..................................................... 26

2.2.3 PCI Express* Ports and Bifurcation ........................................................... 27

2.2.3.1 PCI Express* Bifurcated Mode .................................................... 27

2.3

Direct Media Interface (DMI)............................................................................... 27

2.3.1 DMI Error Flow....................................................................................... 27

2.3.2 Processor/PCH Compatibility Assumptions.................................................. 27

2.3.3 DMI Link Down ...................................................................................... 27

2.4

Platform Environment Control Interface (PECI) ...................................................... 28

2.5

Interface Clocking ............................................................................................. 28

2.5.1 Internal Clocking Requirements................................................................ 28

Technologies

........................................................................................................... 29

3.1

Intel

Virtualization Technology .......................................................................... 29

3.1.1 Intel

VT-x Objectives ............................................................................ 29

3.1.2 Intel

VT-x Features .............................................................................. 29

Datasheet, Volume 1

3.2

3.3

3.4

3.1.3

3.1.4

3.1.5

Intel

VT-d Objectives ............................................................................30

Intel

VT-d Features ...............................................................................30

Intel

VT-d Features Not Supported..........................................................31

Trusted Execution Technology (Intel

TXT) .................................................31

Hyper-Threading Technology .....................................................................32

Turbo Boost Technology ............................................................................32

Power Management

.................................................................................................33

4.1

ACPI States Supported .......................................................................................33

4.1.1 System States........................................................................................33

4.1.2 Processor Core/Package Idle States...........................................................33

4.1.3 Integrated Memory Controller States .........................................................33

4.1.4 PCI Express* Link States .........................................................................34

4.1.5 Interface State Combinations ...................................................................34

4.2

Processor Core Power Management ......................................................................34

4.2.1 Enhanced Intel

SpeedStep

Technology ..................................................34

4.2.2 Low-Power Idle States.............................................................................35

4.2.3 Requesting Low-Power Idle States ............................................................36

4.2.4 Core C-states .........................................................................................37

4.2.4.1 Core C0 State ...........................................................................37

4.2.4.2 Core C1/C1E State ....................................................................37

4.2.4.3 Core C3 State ...........................................................................38

4.2.4.4 Core C6 State ...........................................................................38

4.2.4.5 C-State Auto-Demotion ..............................................................38

4.2.5 Package C-States ...................................................................................38

4.2.5.1 Package C0 ..............................................................................40

4.2.5.2 Package C1/C1E........................................................................40

4.2.5.3 Package C3 State ......................................................................40

4.2.5.4 Package C6 State ......................................................................40

4.3

Integrated Memory Controller (IMC) Power Management.........................................41

4.3.1 Disabling Unused System Memory Outputs.................................................41

4.3.2 DRAM Power Management and Initialization ...............................................41

4.3.2.1 Initialization Role of CKE ............................................................41

4.3.2.2 Conditional Self-Refresh .............................................................41

4.3.2.3 Dynamic Power Down Operation..................................................42

4.3.2.4 DRAM I/O Power Management ....................................................42

4.4

PCI Express* Power Management ........................................................................42

Thermal Management

..............................................................................................43

Signal Description

....................................................................................................45

6.1

System Memory Interface ...................................................................................46

6.2

Memory Reference and Compensation ..................................................................48

6.3

Reset and Miscellaneous Signals ..........................................................................48

6.4

PCI Express* Based Interface Signals ...................................................................49

6.5

DMI—Processor to PCH Serial Interface.................................................................49

6.6

PLL Signals .......................................................................................................50

6.7

Intel

Flexible Display Interface Signals ...............................................................50

6.8

JTAG/ITP Signals ...............................................................................................51

6.9

Error and Thermal Protection...............................................................................52

6.10 Power Sequencing .............................................................................................53

6.11 Processor Core Power Signals ..............................................................................53

6.12 Graphics and Memory Core Power Signals .............................................................55

6.13 Ground and NCTF ..............................................................................................56

6.14 Processor Internal Pull Up/Pull Down ....................................................................56

Datasheet, Volume 1

Electrical Specifications

........................................................................................... 57

7.1

Power and Ground Lands.................................................................................... 57

7.2

Decoupling Guidelines ........................................................................................ 57

7.2.1 Voltage Rail Decoupling........................................................................... 57

7.3

Processor Clocking (BCLK[0], BCLK#[0]) .............................................................. 58

7.3.1 PLL Power Supply ................................................................................... 58

7.4

Voltage Identification (VID) .......................................................................... 58

7.5

Reserved or Unused Signals................................................................................ 62

7.6

Signal Groups ................................................................................................... 62

7.7

Test Access Port (TAP) Connection....................................................................... 65

7.8

Absolute Maximum and Minimum Ratings ............................................................. 65

7.9

DC Specifications .............................................................................................. 66

7.9.1 Voltage and Current Specifications............................................................ 66

7.10 Platform Environmental Control Interface (PECI) DC Specifications........................... 73

7.10.1 DC Characteristics .................................................................................. 73

7.10.2 Input Device Hysteresis .......................................................................... 74

Processor Land and Signal Information

................................................................... 75

8.1

Processor Land Assignments ............................................................................... 75

Datasheet, Volume 1

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