Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Package Information
10 TDFN
Package Code
Outline Number
Land Pattern Number
Thermal Resistance, Single-Layer Board:
Junction-to-Ambient (θ
JA
)
Junction-to-Case Thermal Resistance (θ
JC
)
Thermal Resistance, Four-Layer Board:
Junction-to-Ambient (θ
JA
)
Junction-to-Case Thermal Resistance (θ
JC
)
41°C/W
9°C/W
54°C/W
9°C/W
T1033Y+4C
21-100317
90-0003
For the latest package outline information and land patterns (footprints), go to
www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board.
For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
CC
= +2.9V to +3.5V, V
CL
= V
CC
, 100Ω AC-coupled load between OUTN and OUTP, T
A
= -40°C to +125°C, C
IN
(MAX40660) =
0.5pF (Note 1), C
IN
(MAX40661) = 8pF (Note 1), Input current is defined as flowing out of IN. Typical values are at V
CC
= +3.3V and
T
A
= +25°C, unless otherwise noted.)
PARAMETER
Power Supply Current
V
CL
Quiescent Supply
Current
Input Bias Voltage
Transimpedance
Linearity
V
BIAS
SYMBOL
I
CC
CONDITIONS
LP > 2.0V (logic-high)
LP < 0.8V (logic-low)
LP > 2.0V (logic-high)
LP < 0.8V (logic-low)
IN and OFFSET
GAIN = GND (Note 2)
GAIN = V
CC
(Note 2)
-10
-10
MIN
TYP
41
8
0.1
0.1
0.85
±2
±2
MAX
70
13
20
20
1.0
+10
+10
UNITS
mA
µA
V
%
www.maximintegrated.com
Maxim Integrated | 3
MAX40660/MAX40661
Transimpedance Amplifier with 100mA Input
Current Clamp for Automotive LiDAR
Electrical Characteristics (continued)
(V
CC
= +2.9V to +3.5V, V
CL
= V
CC
, 100Ω AC-coupled load between OUTN and OUTP, T
A
= -40°C to +125°C, C
IN
(MAX40660) =
0.5pF (Note 1), C
IN
(MAX40661) = 8pF (Note 1), Input current is defined as flowing out of IN. Typical values are at V
CC
= +3.3V and
T
A
= +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
Z
21
Transimpedance
CONDITIONS
GAIN logic-low, I
IN
< 2µA
P-P
GAIN logic-high, I
IN
< 1µA
P-P
In low-power standby mode: LP < V
IL,
I
IN
= 1µA
RMS
, f
IN
= 100MHz.
GAIN logic-low, I
OFFSET
< 2µA
P-P
GAIN logic-high, I
OFFSET
< 1µA
P-P
0 to 100mA input current
V
IL
V
IH
I
IL
I
IH
GAIN, LP
GAIN, LP
GAIN, LP
GAIN, LP
Time from LP > V
IL
to output common-
mode voltage 90% of nominal value.
Measured at OUTP and OUTN.
V
CC
-
1.15
ΔV
OUT
Z
OUT
V
OUT(MAX)
R
IN
MAX40661, C
IN
= 10pF (Note 3)
Bandwidth
BW
MAX40661, C
IN
= 5pF (Note 3)
MAX40660, C
IN
= 0.5pF
MAX40661, f = 10MHz, C
IN
= 5pF
Input Noise Density
MAX40661, f = 10MHz, C
IN
= 8pF
MAX40661, f = 10MHz, C
IN
= 10pF
MAX40660, f = 10MHz, C
IN
= 0.8pF
100
130
300
I
IN
= 0mA, GAIN = GND
I
IN
= 0mA, GAIN = V
CC
Single-ended
I
IN
= 0mA to -200µA pulse, GAIN logic-
low
I
IN
= 0mA to -200µA pulse, GAIN logic-
high
40
475
500
-0.3
2.0
±0.001
±0.001
200
V
CC
-
0.73
-200
-400
50
825
920
65
160
200
490
2.5
2.7
3.0
2.1
210
280
660
pA/
√
Hz
pA/Hz
pA/
√
Hz
MHz
60
1290
mV
1490
Ω
V
CC
-
0.40
18
36
MIN
18
36
TYP
25
50
300
25
50
2
+0.8
V
CC
+
0.3
±1.0
±1
µA
µA
ns
V
mV
Ω
32
64
MAX
32
64
UNITS
kΩ
mΩ
kΩ
ns
V
OFFSET Input
Transimpedance
Overload Recovery
Time
Input Logic 0
Input Logic 1
Logic Input Current Low
Logic Input Current High
Standby De-Assert
Delay
Output Common-Mode
Voltage
Differential Output
Offset
Output Impedance
Maximum Differential
Output Voltage Swing
Input Resistance
Note 1:
Limits are 100% tested at T
A
= +25°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization.
Note 2:
Linearity is calculated as follows:
For 25kΩ transimpedance, Linearity = (Large signal gain at 20µA – Large signal gain at 2µA)/Large signal gain at 2µA, where
large signal gain at X is (V
OUT
at I_IN = X - V
OUT
at I_IN = 0)
For 50kΩ transimpedance, Linearity = (Large signal gain at 10µA – Large signal gain at 1µA)/Large signal gain at 1µA, where
large signal gain at X is (V
OUT
at I_IN = X - V
OUT
at I_IN = 0)
Note 3:
-3dB bandwidth is measured relative to the gain at 10MHz.
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