MP20075
3A, 1.05V–3.6V
DDR2/3/3L/4 Memory Termination Regulator
The Future of Analog IC Technology
DESCRIPTION
The
MP20075
precision
DDR2/3/3L/4
termination LDO regulator features a precision
VREF/2
tracking
voltage
for
accurate
termination. The VTT-LDO output can
sink/source up to 3A.
The MP20075 maintains a fast transient
response only requires 20μF (2x10μF) ceramic
output capacitance. The MP20075 supports
Kelvin sensing.
The MP20075 is available in the 8-pin MSOP
with Exposed PAD and is specified from
−40
o
C
to 85
o
C.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
VDDQ Voltage Range: 1.05V to 3.6 V
Up to 3A Integrated Sink/Source Linear
Regulator with Accurate VREF/2 Divider
Reference for DDR2/3/3L/4 Termination
Requires Only 20μF Ceramic Output
Capacitance
Drive Voltage: 3.3V
1.05V Input (VDDQ) Helps Reduce Total
Power Dissipation
Integrated Divider Tracks VREF for
accurate VTT and VTTREF Output Voltage
Kelvin Sensing (VTTSEN)
±30mV Accuracy for VTT
±18mV Accuracy for VTTREF
Built-In Soft-Start, UVLO and OCL
Thermal Shutdown
Notebook DDR2/3/3L/4 Memory Supply
and Termination Voltage in ACPI Compliant
Systems
Active Termination Bus
APPLICATIONS
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP20075 Rev. 1.2
7/15/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
1
MP20075 – 3A, 1.05V-3.6V INPUT, DDR2/3/3L MEMORY TERMINATION REGUALTOR
ORDERING INFORMATION
Part Number*
MP20075DH
Package
MSOP8E
Top Marking
20075
Free Air Temperature (T
A
)
-40°C to +85°C
* For Tape & Reel, add suffix –Z (e.g. MP20075DH–Z);
For RoHS Compliant Packaging, add suffix –LF (e.g. MP20075DH–LF–Z)
PACKAGE REFERENCE
TOP VIEW
DDQ
VTT
GND
VTTSEN
1
2
3
4
8
7
6
5
VTTREF
EN
REF
VDRV
EXPOSED PAD
ON BACKSIDE
ABSOLUTE MAXIMUM RATINGS
(1)
Supply Voltage V
DDQ
........................ -0.3V to 3.6V
Drive Voltage VDRV..................... -0.3V to 6.0V
All Other Pins................................ -0.3V to 6.0V
(2)
Continuous Power Dissipation (T
A
= +25°C)
........................................................... 1.56W
Junction Temperature...............................150
o
C
Lead Temperature ....................................260
o
C
Storage Temperature .............. -50
o
C to +150
o
C
Thermal Resistance
(4)
MSOP8E.................................. 50...... 12...
o
C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature T
J
(MAX), the junction-to-
ambient thermal resistance
θ
JA
, and the ambient temperature
T
A
. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by P
D
(MAX)=(T
J
(MAX)-
T
A
)/
θ
JA
. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its operating
conditions.
4) Measured on JESD51-7 4-layer board.
θ
JA
θ
JC
Recommended Operating Conditions
(3)
Drive Voltage VDRV.................... 3.0V to 3.5V
Operating Junct. Temp (T
J
) .......-40
o
C to +125
o
C
MP20075 Rev. 1.2
7/15/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
2
MP20075 – 3A, 1.05V-3.6V INPUT, DDR2/3/3L MEMORY TERMINATION REGUALTOR
ELECTRICAL CHARACTERISTICS
Parameters
Symbol
V
DRV
= 3.3V, T
A
= +25
o
C, unless otherwise noted.
Test Condition
ITT=3A
VDRV =3.3 V, VDDQ=0V
VEN_H, VTT=0.75V
Min
3.0
Typ
3.3
0.2
1.3
150
25
0.9
-30
-30
-30
-30
-30
-30
4.0
4.0
1.0
VREF=1.8, VDRV=3.3V
VREF=1.5V, VDRV=3.3V
VREF = 1.8 V or 1.5 V
1/2VREF – VTTR,
VREF = 1.8 V,
IVTTR = 0mA to 10mA
1/2VREF – VTTR,
VREF = 1.5 V,
IVTTR = 0mA to 10mA
10
-18
18
9
7
Max
3.5
1.0
3
Unit
V
μA
mA
o
C
o
C
V
mV
VDRV Operating Voltage
VDRV
VDRV Shut down current
IDRV_SD
VDRV Operation Current
IDRV
Thermal Trip Point
TSD
Hysteresis
TSDHYS
VDDQ
UVLO
Upper
VDDQUV+
Threshold
Rising Edge; hysteresis = 55mV
1/2VREF – VTT, VREF = 1.8V,
IVTT = 0 to 3A (Sink Current)
IVTT = 0 to 3A (Source Current)
1/2VREF – VTT, VREF = 1.5V,
IVTT = 0 to 3A (Sink Current)
IVTT = 0 to 3A (Source Current)
1/2VREF -VTT, VREF=1.35V
IVTT = 0 to 3A (Sink Current)
IVTT = 0 to 3A (Source Current)
1.0
30
30
30
30
30
30
VTT with Respect to 1/2VREF
dVTT0
mV
mV
A
A
A
μs
mA
mV
Source Current Limit
Sink Current Limit
Soft−Start
Limit
Source
Current
ILIMVTsrc
ILIMVTsnk
ILIMVTSS
tssvttmax
IVTTR
Maximum Soft−Start Time
VTTREF Source Current
VTTREF Accuracy Referred
to 1/2VREF
dVTTR
-15
1.4
15
mV
V
EN Pin Threshold High
EN Pin Threshold Low
EN Pin Input Current
EN_H
EN_L
IIN_EN
EN = 3.3 V
0.5
1.0
V
μA
MP20075 Rev. 1.2
7/15/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
3
MP20075 – 3A, 1.05V-3.6V INPUT, DDR2/3/3L MEMORY TERMINATION REGUALTOR
PIN FUNCTIONS
Pin #
1
2
3
4
5
6
7
8
Name
DDQ
VTT
GND,
Exposed
Pad
VTTSEN
VDRV
REF
EN
VTTREF
Description
Power input for VTT regulator. Bypass with a 10μF ceramic capacitor. It is normally
connected to the VDDQ of DDR2/3/3L/4 memory rail.
Power output for the VTT LDO. Output is a precision VREF/2 voltage that tracks VREF.
Recommended bypass is 2x10μF ceramic capacitors.
The exposed pad and GND pin must be connected to the same ground plane.
Kelvin sensed feedback signal.
Chip bias Voltage. Connect to 3.3V supply and bypass with a 4.7μF capacitor.
LDO signal input for generating VDDQ/2 reference. Bypass with a 0.1μF capacitor.
VTT regulator enable input. EN HIGH will enable the MP20075 requires 100k pull-up
resistor.
Precision buffered output for the system with a drive capability up to 10mA. The receiving
end of the DDR2/3/3L/4 memory cells requires this signal for their input comparator.
Bypass with a 0.1μF capacitor.
MP20075 Rev. 1.2
7/15/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
4
MP20075 – 3A, 1.05V-3.6V INPUT, DDR2/3/3L MEMORY TERMINATION REGUALTOR
TYPICAL PERFORMANCE CHARACTERISTICS
V
TTREF
Regulation
0.91
0.9
0.89
0.88
0.87
0.86
C
1
=C
2
= C
3
=10μF, C
4
=C
6
=0.1μF, C
7
=4.7μF, V
DRV
=3.3V, T
A
=25
o
C, unless otherwise noted.
DDR2 Regulation
0.96
0.94
0.92
0.90
0.88
0.86
-4
0.81
0.79
0.77
0.75
0.73
0.71
-4
DDR3 Regulation
0
4
8
12
16
20
-3
-2
-1
0
1
2
3
4
-3
-2
-1
0
1
2
3
4
LOAD CURRENT (A)
LOAD CURRENT (A)
3.0
2.5
2.0
1.5
1.0
0.5
-40
0.905
0.903
0.901
0.899
0.897
0.895
-40
0.755
0.753
0.751
0.749
0.747
0.745
-40
-10
20
50
80
110
-10
20
50
80
110
-10
20
50
80
110
V
TT
20mV/div.
V
TT
20mV/div.
V
DRV
2V/div.
V
DDQ
2V/div.
V
TT
0.5V/div.
I
TT
2A/div.
I
TT
2A/div.
I
TT
2A/div.
MP20075 Rev. 1.2
7/15/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
5
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