EEWORLDEEWORLDEEWORLD

Part Number

Search

TSC80C51TXXX-16IF

Description
CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size279KB,19 Pages
ManufacturerTEMIC
Websitehttp://www.temic.de/
Download Datasheet Parametric View All

TSC80C51TXXX-16IF Overview

CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller

TSC80C51TXXX-16IF Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerTEMIC
Reach Compliance Codeunknow
Has ADCNO
Address bus width16
bit size8
CPU series8051
maximum clock frequency16 MHz
DAC channelNO
DMA channelNO
External data bus width8
JESD-30 codeS-PQFP-G44
JESD-609 codee0
Number of I/O lines32
Number of terminals44
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
PWM channelNO
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeTQFP44,.47SQ,32
Package shapeSQUARE
Package formFLATPACK
power supply5 V
Certification statusNot Qualified
RAM (bytes)128
rom(word)4096
ROM programmabilityMROM
speed16 MHz
Maximum slew rate19.4 mA
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationQUAD
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER
versions of the 8051 NMOS single chip 8 bit
µC.
The fully static design of the TSC80C31/80C51 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TSC80C31/80C51 retains all the features of the 8051
: 4 K bytes of ROM ; 128 bytes of RAM ; 32 I/O lines ;
two 16 bit timers ; a 5-source, 2-level interrupt structure
; a full duplex serial port ; and on-chip oscillator and clock
circuits.
software-selectable modes of reduced activity for further
reduction in power consumption. In the Idle Mode the
CPU is frozen while the RAM, the timers, the serial port,
and the interrupt system continue to function. In the
Power Down Mode the RAM is saved and all other
functions are inoperative.
The TSC80C31/80C51 is manufactured using SCMOS
process which allows them to run from 0 up to 44 MHz
with VCC = 5 V. The TSC80C31/80C51 is also available
at 20 MHz with 2.7 V < Vcc < 5.5 V.
D
TSC80C31/80C51-L16 : Low power version
Vcc : 2.7–5.5 V Freq : 0–16 MHz
D
TSC80C31/80C51-L20 : Low power version
Vcc : 2.7–5.5 V Freq : 0–20 MHz
D
TSC80C31/80C51-12 : 0 to 12 MHz
D
TSC80C31/80C51-20 : 0 to 20 MHz
D
TSC80C31/80C51-25 : 0 to 25 MHz
D
D
D
D
TSC80C31/80C51-30 : 0 to 30 MHz
TSC80C31/80C51-36 : 0 to 36 MHz
TSC80C31/80C51-40 : 0 to 40 MHz
TSC80C31/80C51-44 : 0 to 44 MHz*
* Commercial and Industrial temperature range only. For other speed
and range please consult your sale office.
Features
D
D
D
D
D
D
D
Power control modes
128 bytes of RAM
4 K bytes of ROM (TSC80C31/80C51)
32 programmable I/O lines
Two 16 bit timer/counter
64 K program memory space
64 K data memory space
D
D
D
D
D
D
Fully static design
0.8
µm
CMOS process
Boolean processor
5 interrupt sources
Programmable serial port
Temperature range : commercial, industrial, automotive and
military
Optional
D
Secret ROM : Encryption
D
Secret TAG : Identification number
MATRA MHS
Rev. E (14 Jan.97)
1
CE5.0 debug version NK compilation error!
I have never used the DEBUG version of NK. Today, after compiling, an error occurred: kitl.lib(ethdbg.obj) : error LNK2001: unresolved external symbol dpCurSettings. This error occurred when compiling...
dm29769671 Embedded System
2009 The saddest year
iSuppli, a market research organization, released a preliminary statistical report on the top 20 semiconductor manufacturers in the world in 2009. Although the entire industry is gloomy, only one of t...
西点 FPGA/CPLD
Questions about the 2x in-phase proportional operational amplifier composed of OPA380
As shown in the figure, there are two questions: 1. Why is the amplitude-frequency gain in the Bode plot not 6dB, but slightly greater than 6dB (6.02dB, as shown in the blue box in the figure)? Is it ...
xiaxingxing Analog electronics
Increase performance in imaging applications by integrating DSP functions in FPGAs
This article describes the development of an embedded system for a small, high-performance, ultra-low-cost camera. Initially, a digital signal processor, several ASSPs, and external memory were used. ...
lorant FPGA/CPLD
Upload an ST-LINK firmware update software
I found it online. My ST-LINK was very old. The new version of MDK said that my firmware was old. I found this on the Internet. It is now old. I can use ST-LINK under MDK4.6. I dare not keep it to mys...
ddllxxrr stm32/stm8
Helper2416-18——Ninth Bare Metal Part——MMU & Exception Handling Practice + Practice Source Code
[i=s]This post was last edited by yuanlai2010 on 2014-7-23 20:52[/i] [align=center][b][font=楷体, 楷体_GB2312][size=5][color=#0000ff]Nine Parts of Bare Metal - MMU & Exception Handling Practice[/color][/s...
yuanlai2010 Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1890  585  1030  1418  2509  39  12  21  29  51 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号