Replaces X25323/X25325
X5323/X5325
CPU Supervisor with 32Kb SPI EEPROM
FEATURES
• Selectable watchdog timer
• Low V
CC
detection and reset assertion
—Five standard reset threshold voltages
—Re-program low V
CC
reset threshold voltage
using special programming sequence
—Reset signal valid to V
CC
= 1V
• Determine watchdog or low voltage reset with a
volatile flag bit
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 32Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lock
™
protection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14-lead TSSOP, 8-lead SOIC
BLOCK DIAGRAM
Watchdog Transition
Detector
WP
SI
SO
SCK
CS/WDI
Data
Register
Command
Decode &
Control
Logic
V
CC
Threshold
Reset Logic
Protect Logic
RESET/RESET
Status
Register
8Kbits
8Kbits
16Kbits
EEPROM Array
Reset &
Watchdog
Timebase
X5323 = RESET
X5325 = RESET
Watchdog
Timer Reset
DESCRIPTION
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when V
CC
falls below the minimum V
CC
trip
point. RESET/RESET is asserted until V
CC
returns to
proper operating level and stabilizes. Five industry stan-
dard V
TRIP
thresholds are available, however, Xicor’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
V
CC
V
TRIP
+
-
Power On and
Low Voltage
Reset
Generation
REV 1.1.2 11/13/01
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Characteristics subject to change without notice.
1 of 21
X5323/X5325
PIN CONFIGURATION
14-Lead TSSOP
8-Lead SOIC/PDIP
CS/WDT
SO
WP
V
SS
1
2
3
4
X5323/25
8
7
6
5
V
CC
RESET/RESET
SCK
SI
CS/WDT
SO
NC
NC
NC
WP
V
SS
1
2
3
4
5
6
7
X5323/25
14
13
12
11
10
9
8
V
CC
RESET/RESET
NC
NC
NC
SCK
SI
PIN DESCRIPTION
Pin
(SOIC/PDIP)
1
Pin
TSSOP
1
Name
CS/WDI
Function
Chip Select Input.
CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the
device will be in the standby power mode. CS LOW enables the device, placing
it in the active power mode. Prior to the start of any operation after power up, a
HIGH to LOW transition on CS is required.
Watchdog Input.
A HIGH to LOW transition on the WDI pin restarts the watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock.
The serial clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or data bits present
on the SI pin. The falling edge of SCK changes the data output on the SO pin.
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the watchdog timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output
. RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever V
CC
falls below the minimum V
CC
sense level. It
will remain active until V
CC
rises above the minimum V
CC
sense level for
200ms. RESET/RESET goes active if the watchdog timer is enabled and CS
remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes
active on power up at about 1V and remains active for 200ms after the power
supply stabilizes.
No internal connections
2
5
2
8
SO
SI
6
9
SCK
3
4
8
7
6
7
14
13
WP
V
SS
V
CC
RESET/
RESET
3-5,10-12
NC
REV 1.1.2 11/13/01
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Characteristics subject to change without notice.
2 of 21
X5323/X5325
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X5323/X5325 activates a
power on reset circuit. This circuit goes active at about
1V and pulls the RESET/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
of the oscillator. As long as RESET/RESET pin is active,
the device will not respond to any Read/Write instruc-
tion. When V
CC
exceeds the device V
TRIP
value for
200ms (nominal) the circuit releases RESET/RESET,
allowing the processor to begin executing code.
Low Voltage Monitoring
During operation, the X5323/X5325 monitors the V
CC
level and asserts RESET/RESET if supply voltage falls
below a preset minimum V
TRIP
. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
CC
returns and exceeds
V
TRIP
for 200ms.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET/RESET signal. The CS/WDI pin must be tog-
gled from HIGH to LOW prior to the expiration of the
watchdog time out period. The state of two nonvolatile
control bits in the status register determine the watch-
dog timer period. The microprocessor can change these
watchdog bits, or they may be “locked” by tying the WP
pin LOW and setting the WPEN bit HIGH.
V
CC
Threshold Reset Procedure
The X5323/X5325 has a standard V
CC
threshold
(V
TRIP
) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard V
TRIP
is not exactly right, or
for higher precision in the V
TRIP
value, the X5323/
X5325 threshold may be adjusted.
Setting the V
TRIP
Voltage
This procedure sets the V
TRIP
to a higher voltage
value. For example, if the current V
TRIP
is 4.4V and the
new V
TRIP
is 4.6V, this procedure directly makes the
SCK
V
P
SI
change. If the new setting is lower than the current set-
ting, then it is necessary to reset the trip point before
setting the new value.
To set the new V
TRIP
voltage, apply the desired V
TRIP
threshold to the Vcc pin and tie the CS/WDI pin and the
WP pin HIGH. RESET/RESET and SO pins are left
unconnected. Then apply the programming voltage V
P
to both SCK and SI and pulse CS/WDI LOW then
HIGH. Remove V
P
and the sequence is complete.
Figure 1. Set V
TRIP
Voltage
CS
V
P
Resetting the V
TRIP
Voltage
This procedure sets the V
TRIP
to a “native” voltage
level. For example, if the current V
TRIP
is 4.4V and the
V
TRIP
is reset, the new V
TRIP
is something less than
1.7V. This procedure must be used to set the voltage to
a lower value.
To reset the V
TRIP
voltage, apply a voltage between
2.7 and 5.5V to the V
CC
pin. Tie the CS/WDI pin, the
WP pin, and the SCK pin HIGH. RESET/RESET and
SO pins are left unconnected. Then apply the program-
ming voltage V
P
to the SI pin ONLY and pulse CS/WDI
LOW then HIGH. Remove V
P
and the sequence is
complete.
Figure 2. Reset V
TRIP
Voltage
CS
V
CC
SCK
V
P
SI
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Characteristics subject to change without notice.
3 of 21
X5323/X5325
Figure 3. V
TRIP
Programming Sequence Flow Chart
V
TRIP
Programming
Execute
Reset V
TRIP
Sequence
Set V
CC
= V
CC
Applied =
Desired V
TRIP
New V
CC
Applied =
Old V
CC
Applied + Error
Execute
Set V
TRIP
Sequence
New V
CC
Applied =
Old V
CC
Applied - Error
Apply 5V to V
CC
Execute
Reset V
TRIP
Sequence
Decrement V
CC
(V
CC
= V
CC
- 10mV)
NO
RESET pin
goes active?
YES
Error
≤
Emax
Error
≥
Emax
Measured V
TRIP
-
Desired V
TRIP
Error < Emax
Emax = Maximum Desired Error
DONE
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Characteristics subject to change without notice.
4 of 21
X5323/X5325
Figure 4. Sample V
TRIP
Reset Circuit
V
P
4.7K
NC
V
TRIP
Adj.
Program
+
1
8
2
7
X5323/25
3
6
4
5
NC
NC
4.7K
RESET
10K
10K
Reset V
TRIP
Test V
TRIP
Set V
TRIP
SPI SERIAL MEMORY
The memory portion of the device is a CMOS serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software proto-
col allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
™
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
All instructions (Table 1), addresses and data are trans-
ferred MSB first. Data input on the SI line is latched on
the first rising edge of SCK after CS goes LOW. Data is
output on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start it
again to resume operations where left off.
Table 1. Instruction Set
Instruction Name
WREN
SFLB
WRDI/RFLB
RSDR
WRSR
READ
WRITE
Note:
Write Enable Latch
The device contains a write enable latch. This latch
must be SET before a write operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid write cycle.
Status Register
The RDSR instruction provides access to the status reg-
ister. The status register may be read at any time, even
during a write cycle. The status register is formatted as
follows:
7
WPEN
6
FLB
5
4
3
BL1
2
BL0
1
WEL
0
WIP
WD1 WD0
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a non-
volatile write operation is in progress. When set to a
“0”, no write is in progress.
Instruction Format*
0000 0110
0000 0000
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set flag bit
Operation
Set the write enable latch (enable write operations)
Reset the write enable latch/reset flag bit
Read status register
Write status register (watchdog, block lock, WPEN & flag bits)
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
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Characteristics subject to change without notice.
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