H8S/2355 Series
HD6432355, HD6472355
H8S/2353
HD6432353
H8S/2393
HD6432393
Hardware Manual
ADE-602-112B
Rev. 3.0
2/29/00
Hitachi, Ltd
Cautions
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have received the latest product standards or specifications before final design, purchase or
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However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
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life support.
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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
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consider normally foreseeable failure rates or failure modes in semiconductor devices and
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Preface
The H8S/2355 Series is a series of high-performance microcontrollers with a 32-bit H8S/2000
CPU core, and a set of on-chip supporting functions required for system configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
On-chip memory consists of large-capacity ROM and RAM. PROM (ZTAT™*) and mask ROM
versions are available, providing a quick and flexible response to conditions from ramp-up through
full-scale volume production, even for applications with frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), 8-bit timers, watchdog timer
(WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports.
An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transfer
without CPU intervention.
Use of the H8S/2355 Series enables compact, high-performance systems to be implemented easily.
This manual describes the hardware of the H8S/2355 Series. Refer to the H8S/2600 Series and
H8S/2000 Series Programming Manual for a detailed description of the instruction set.
Note: * ZTAT is a trademark of Hitachi, Ltd. There is no PROM version of the H8S/2393.
Main Revisions and Additions in This Edition
Page
All
4
Table 1-1 Overview Product lineup
Section
Revision Contents
H8S/2393 added
[Amendments]
Amendments associated with H8S/2393
addition
6
9, 10
Figure 1-2 Block Diagram (H8S/2393)
Figure 1-5 H8S/2393 Pin Arrangement
(TFP-120: Top View)
Figure 1-6 H8S/2393 Pin Arrangement
(TFP-128: Top View)
81, 82
225
Figure 3-3 Memory Map in Each Operating [Addition]
Mode in the H8S/2393
8.5.1 Overview (Port 4)
[Amendment]
Port 4 pins also function ..... as A/D converter
analog input pins (AN0 to AN7) in the
H8S/2393.
421
Table 12-3 BRR Settings for Various Bit
Rates (Asynchronous Mode)
Bit Rate: 38400
14.2.3
A/D Control Register (ADCR)
Description of bits 7 and 6
[Amendment]
“Error” entries when ø = 4 MHz amended to
“—”.
[Amendment]
Bit 7
Bit 6
TRGS1 TRGS0 Description
0
0
1
1
0
1
A/D conversion start by external trigger is disabled (Initial value)
A/D conversion start by external trigger (TPU) is enabled
A/D conversion start by external trigger (8-bit timer) is enabled
A/D conversion start by external trigger pin (ADTRG) is enabled
[Addition]
[Addition]
502
Table 14.6 Analog Pin Specifications
517
Section 15 D/A Converter
[Deletion]
[Amendment]
(Not supported in H8S/2393)
533
Figure 17-2 Wiring of 120-Pin/32-Pin
Socket Adapter
Pin 4 of FP-128
[Amendment]
Changed to “Open”.
558
Table 19-3 MSTP Bits and Corresponding [Addition]
On-Chip Supporting Modules
*
In the H8S/2393 bit 10 can be read and
Bit MSTP10
written to but has no effect on operation,
as a D/A converter is not supported.
Page
570
Section
Table 20-2 DC Characteristics (3)
Revision Contents
[Additions]
DC characteristics added for following
conditions.
Conditions: V
CC
= 3.0 to 5.5 V, AV
CC
= 3.0 to
5.5 V, V
ref
= 3.0 V to AV
CC
, V
SS
=
AV
SS
= 0 V*
1
, T
a
= –20 to +75°C
(regular specifications),
T
a
= –40 to +85°C (wide-range
specifications)
574
576
578
586
591
592
Table 20-4 Clock Timing
Table 20-5 Control Signal Timing
Table 20-6 Bus Timing
[Additions]
Additions for Condition C
Condition C: (mask ROM version only)
V
CC
= 3.0 to 5.5 V, AV
CC
= 3.0 to
Table 20-7 Timing of On-Chip Supporting
5.5 V, V
ref
= 3.0 V to AV
CC
,
Modules
V
SS
= AV
SS
= 0 V, ø = 2 to 13
Table 20-8 A/D Conversion Characteristics
MHz, T
a
= –20 to +75°C
(regular specifications),
Table 20-9 D/A Conversion Characteristics
T
a
= –40 to +85°C (wide-range
specifications)
Table A-5
Number of Cycles in Instruction [Amendments]
Execution
2n + 2*
2
EEPMOV instruction, Byte Data
Note: 2. When n bytes of data are
Access
transferred.
[Amendments]
4
642
672
B.1 Addresses
H’FFA4
H’FFA5
H’FFA6
DADR0*
4
DADR1*
DACR*
4
Note: 4. In the H8S/2393 these bits are
reserved, as a D/A converter is not
supported.
[Deletion]
Note:
*
Priority order: Output compare
output/PWM output > DR output
781
to
785
Figure C-1 (a) Port 1 Block Diagram
(Pins P1
0
, P1
1
, P1
4
and P1
6
)
Figure C-1 (b) Port 1 Block Diagram
(Pins P1
2
, P1
3
, P1
5
, and P1
7
)
Figure C-2 (a) Port 2 Block Diagram
(Pins P2
0
and P2
1
)
Figure C-2 (b) Port 2 Block Diagram
(Pins P2
2
and P2
4
)
Figure C-2 (c) Port 2 Block Diagram
(Pins P2
3
and P2
5
)
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