DISCRETE SEMICONDUCTORS
DATA SHEET
BS208
P-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
FEATURES
•
Direct interface to C-MOS
•
High-speed switching
•
No secondary breakdown.
DESCRIPTION
P-channel enhancement mode
vertical D-MOS transistor in a TO-92
envelope. Intended for use in relay,
high-speed and line transformer
drivers.
PINNING - TO-92
PIN
1
2
3
DESCRIPTION
source
gate
drain
MAM149
BS208
handbook, halfpage
1
d
2
3
g
s
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
V
DS
V
GSO
Y
fs
I
D
R
DS(on)
P
tot
PARAMETER
drain-source voltage (DC)
gate-source voltage (DC)
forward transfer admittance
drain current (DC)
drain-source on-state resistance V
GS
=
−10
V; I
D
=
−200
mA
total power dissipation
T
amb
= 25
°C
open drain
I
D
=
−200
mA; V
DS
=
−25
V
CONDITIONS
−
−
100
−
−
−
MIN.
−
−
200
−
10
−
TYP.
MAX.
−200
±20
−
−0.2
14
0.83
V
V
mS
A
Ω
W
UNIT
April 1995
2
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134)
SYMBOL
−V
DS
±V
GSO
−I
D
−I
DM
P
tot
T
stg
T
j
PARAMETER
drain-source voltage
gate-source voltage
drain current
drain current
total power dissipation
storage temperature range
junction temperature
open drain
DC
peak value
T
amb
= 25
°C
CONDITIONS
MIN.
−
−
−
−
−
−65
−
MAX.
200
20
0.2
0.6
BS208
UNIT
V
V
A
A
W
°C
°C
0.83
+150
150
THERMAL RESISTANCE
SYMBOL
R
thj-a
PARAMETER
from junction to ambient
MAX.
150
K/W
UNIT
handbook,
1
MDA690
Ptot
(W)
0.8
0.6
0.4
0.2
0
0
50
100
150
200
Tamb (°C)
Fig.2 Power derating curve.
April 1995
3
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified.
SYMBOL
−V
(BR)DSS
−I
DSS
−I
DSS
−I
GSS
−V
GS(th)
R
DS(on)
Y
fs
C
iss
C
oss
C
rss
t
on
t
off
Notes
1. Measured at f = 1 MHz;
−V
DS
= 25 V; V
GS
= 0.
2.
−V
GS
= 0 to 10 V;
−I
D
= 250 mA;
−V
DD
= 50 V.
PARAMETER
drain-source breakdown
voltage
drain-source leakage current
drain-source leakage current
gate-source leakage current
gate-source threshold
voltage
drain-source on-resistance
transfer admittance
input capacitances
output capacitance
feedback capacitance
turn-on time
turn-off time
CONDITIONS
−V
GS
= 0
−I
D
= 10
µA
−V
DS
= 130 V
V
GS
= 0
−V
DS
= 70 V
−V
GS
= 0.2 V
−V
GS
= 20 V
V
DS
= 0
V
GS
= V
DS
−I
D
= 1 mA
−V
GS
= 10 V
−I
D
= 200 mA
−V
DS
= 25 V
−I
D
= 200 mA
note 1
note 1
note 1
note 2
note 2
MIN.
200
−
−
−
0.8
−
100
−
−
−
−
−
TYP.
−
−
−
−
−
−
200
55
20
5
5
20
MAX.
-
1
25
100
2.8
14
−
90
30
15
10
30
BS208
UNIT
V
µA
µA
nA
V
Ω
mS
pF
pF
pF
ns
ns
handbook, halfpage
VDD =
−50
V
handbook, halfpage
10 %
INPUT
90 %
0V
−10
V
ID
50
Ω
MBB689
10 %
OUTPUT
90 %
ton
toff
MBB690
Fig.3 Switching times test circuit.
Fig.4 Input and output waveforms.
April 1995
4
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
BS208
handbook, halfpage
−1
MDA706
ID
VGS =
−10
V
−6
V
handbook, halfpage
−1
MDA707
(A)
−0.8
ID
(A)
−0.8
−0.6
−5
V
−0.6
−0.4
−4
V
−0.2
−3
V
0
0
−5
−10
−15
−20
−25
VDS (V)
−0.4
−0.2
0
0
−2
−4
−6
−8
−10
VGS (V)
Fig.5 Typical output characteristics; T
j
= 25
°C.
Fig.6
Typical transfer characteristics;
V
DS
=
−10
V; T
j
= 25
°C.
handbook, halfpage
−10
3
MDA708
VGS =
−10
V
−5
V
handbook, halfpage
160
MDA709
C
(pF)
120
ID
(mA)
−4
V
−10
2
80
Ciss
40
Coss
Crss
−10
0
8
12
16
20
24
28
RDSon (Ω)
0
−5
−10
−15
−20
−25
VDS (V)
Fig.7
Typical on-resistance as a function of drain
current; T
j
= 25
°C.
Fig.8
Typical capacitances as a function of
drain-source voltage; V
GS
= 0; f = 1 MHz;
T
j
= 25
°C.
April 1995
5
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