V62C3802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
• Low-power consumption
- Active: 40mA at 35ns
- Stand-by: 10
µA
(CMOS input/output)
2
µA
CMOS input/output, L version
• Single + 2.7 to 3.3V Power Supply
• Equal access and cycle time
• 35/45/55/70/85/100 ns access time
• Easy memory expansion with CE1, CE2
and OE inputs
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
• Package available: 32-TSOP1 / STSOP
• 48 Ball CSP_BGA
Logic Block Diagram
Functional Description
The V62C3802048L is a low power CMOS Static RAM orga-
nized as 262,144 words by 8 bits. Easy memory expansion is p-
rovided by an active LOW CE1, an active HIGH CE2, an acti-
ve LOW OE , and Tri-state I/O’s. This device has an autom-
atic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip En-
able 1 (CE1) with Write Enable (WE ) LOW, and Chip Enab-
le 2 (CE2) HIGH. Reading from the device is performed by
taking Chip Enable 1 (CE1) with Output Enable (OE)
LOW while Write Enable (WE ) and Chip Enable 2 (CE2)
is HIGH. The I/O pins are placed in a high-impedance sta-
te when the device is deselected: the outputs are disabled d-
uring a write cycle.
The V62C3802048LL comes with a 1V data retention feature
and Lower Standby Power. The V62C3802048L is available in
a 32-pin 8 x 20 mm TSOP1/8 x 13.4mm STSOP and CSP type
48-fpBGA packages.
32-Pin TSOP1 / STSOP(CSP_BGA see next page)
A
11
A
9
A
8
INPUT BUFFER
ROW DECODER
SENSE AMP
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A9
I/O8
A
13
WE
CE
2
A
15
Vcc
A17
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
GND
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
A
3
Cell Array
I/O1
COLUMN DECODER
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
CONTROL
CIRCUIT
OE
WE
CE1
CE2
1
REV. 1.2
May
2001 V62C3802048L(L)
V62C3802048L(L)
Absolute Maximum Ratings *
Parameter
Voltage on Any Pin Relative to Gnd
Power Dissipation
Storage Temperature (Plastic)
Temperature Under Bias
Symbol
Vt
P
T
Tstg
Tbias
Minimum
-0.5
−
-55
-40
Maximum
4.6
1.0
+150
+85
Unit
V
W
0
C
0
C
* Note:
Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth Table
CE1
H
X
L
L
L
CE2
X
L
H
H
H
WE
X
X
H
H
L
OE
X
X
L
H
X
Data
High-Z
High-Z
Data Out
High-Z
Data In
Standby
Standby
Active, Read
Mode
Active, Output Disable
Active, Write
* Key:
X = Don’t Care, L = Low, H = High
Recommended Operating Conditions
(T
A
= 0
0
C to +70
0
C / -40
0
C to 85
0
C
**
)
Parameter
Supply Voltage
Symbol
V
CC
Gnd
V
IH
V
IL
Min
2.7
0.0
2.2
-0.5*
Typ
3.0
0.0
-
-
Max
3.3
0.0
V
CC
+ 0.2
0.6
Unit
V
V
V
V
Input Voltage
*
V
IL
min = -2.0V for pulse width less than t
RC
/2.
**
For Industrial Temperature.
3
REV. 1.2
May
2001 V62C3802048L(L)
V62C3802048L(L)
DC Operating Characteristics
(V
cc
= 2.7 to 3.3V, Gnd = 0V, T
A
= 0
0
C to +70
0
C / -40
0
C to 85
0
C)
Parameter
Input Leakage Current
Output Leakage
Current
Operating Power
Supply Current
Average Operating
Current
Sym
Test Conditions
V
cc
= Max,
V
in
= Gnd to V
cc
CE1 = V
IH
or CE2 = V
IL
V
cc
= Max, V
OUT
= Gnd to V
cc
CE1 = V
IL
, CE2 = V
IH
V
IN
= V
IH
or V
IL
, I
OUT
= 0 mA
CE1 = V
IL
, CE2 = V
IH
I
OUT
= 0mA,
Min Cycle, 100% Duty
CE1 = 0.2V ,
CE2 =V
cc
- 0.2V
I
OUT
= 0mA,
-55
-
-
-
-
1
1
3
35
-
-
-
-
-70
1
1
3
35
-
-
-
-
-85
1
1
3
30
-
-
-
-
-100
1
1
3
25
Min Max Min Max Min Max Min Max
Unit
µA
µA
I
I
LI
I
I
I
LO
I
I
CC
I
CC1
mA
mA
I
CC2
-
3
-
3
-
3
-
3
mA
Cycle Time=1µs, 100% Duty
Standby Power Supply
Current (TTL Level)
Standby Power Supply
Current (CMOS Level)
I
SB
I
SB1
CE1 = V
IH
or CE2 = V
IL
CE1 > V
cc
- 0.2V or
CE2 < 0.2V, f = 0
V
IN
< 0.2V or
V
IN
> V
cc
- 0.2V
I
OL
= 2 mA
I
OH
= -2 mA
-
-
0.5
10
2
0.4
-
-
-
-
-
2.4
0.5
10
2
0.4
-
-
-
-
-
2.4
0.5
10
2
0.4
-
-
-
-
-
2.4
0.5
10
2
0.4
-
mA
µA
µA
L
-
-
2.4
Output Low Voltage
Output High Voltage
V
OL
V
OH
V
V
Capacitance
(f = 1MHz, T
A
= 25
0
C)
Parameter*
Symbol
Input Capacitance
I/O Capacitance
Test Condition
V
in
= 0V
V
in
= V
out
= 0V
Max
7
8
Unit
pF
pF
C
in
C
I/O
* This parameter is guaranteed by device characterization and is not production tested.
AC Test Conditions
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing
Reference Level
0.6V to 2.2V
5ns
50% of input level
(VIL+VIH)/2
C
L
*
Output Load Condition
70ns/85 ns
C
L
= 30pf + 1TTL Load
Load 100ns/120 ns
C
L
= 100pf + 1TTL Load
Figure A.
* Including Scope and Jig Capacitance
4
REV. 1.2
May
2001 V62C3802048L(L)
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