EEWORLDEEWORLDEEWORLD

Part Number

Search

531BA1313M00DG

Description
LVDS Output Clock Oscillator, 1313MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531BA1313M00DG Overview

LVDS Output Clock Oscillator, 1313MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531BA1313M00DG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTRAY
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency1313 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVDS
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Multi-cell 36-48V Battery Management System Reference Design
[i=s]This post was last edited by qwqwqw2088 on 2019-12-4 08:29[/i]The TI design presented here provides monitoring, balancing, primary protection and gauging for 12- to 15-cell lithium-ion or lithium...
qwqwqw2088 Analogue and Mixed Signal
Implementation Rules of the 2010 Intel Cup Undergraduate Electronic Design Competition Embedded System Invitational Competition
[i=s]This post was last edited by paulhyde on 2014-9-15 08:59[/i] 1. Training and registration of participating students1. The time of this special invitation competition starts from March 18, 2010 an...
open82977352 Electronics Design Contest
I have two problems encountered in debugging ultrasonic ranging. Please give me some guidance.
I used the typical 89C52 MCU control + 74LS04 drive transmission + CX20106 receiver circuit on the Internet. There is no problem with welding, and the distance measurement can be achieved. But the max...
立志成为EEer 51mcu
EBAZ4205 mining board transformation based on Z7010
[i=s]This post was last edited by chenzhufly on 2019-6-11 00:32[/i]The main changes were to the power supply, adding a serial port and JTAG for easier debugging. As for the SD card, there is no plan t...
chenzhufly FPGA/CPLD
Discuss what issues need to be paid attention to when porting 51 programs to 430
[b][size=3][color=#000000]#define DS1302_IN P2IN #define DS1302_OUT P2OUT #define DS1302_RST BIT1 #define DS1302_SCLK BIT0 #define DS1302_SDI BIT2 //Define the port of MSP320 #define DS1302_RST_LO DS1...
fish001 Microcontroller MCU
FPGA Design Lessons Learned
I have been working on FPGA design for a while. I have experienced the joy of solving problems and the pain of searching for results and answers. Now I will summarize the problems and mistakes I often...
loca FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 990  363  1379  2839  1238  20  8  28  58  25 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号