FPGA Design Lessons Learned

loca

FPGA Design Lessons Learned [Copy link]

I have been working on FPGA design for a while. I have experienced the joy of solving problems and the pain of searching for results and answers. Now I will summarize the problems and mistakes I often encountered in projects. I hope it will be inspiring and helpful to everyone: 1) The timing of the interface between FPGA and other circuits should be handled well, and the line delay before the signal enters the FPGA should be considered. The phase relationship between the data and clock entering the FPGA should be clear. 2) If there is a full digital phase-locked loop in the FPGA design, then use an oscilloscope to test whether the full digital phase-locked loop is locked. Ensure that the full digital phase-locked loop works normally. 3) For large fan-out signals, try to use global clock resources. 4) If the system clock frequency is high, try to use synchronous design. 5) If you check the code and hardware circuit for a long time without success, then check whether there is an error in the pin assignment of your FPGA. A project I worked on a few days ago had an SRAM address line assigned incorrectly. I was depressed for more than a week.

kailan818

Let others avoid detours:victory:

lixiaod2008

:victory: :handshake

guo159357

4734.pdf :time::time:

676748500

SOSO is really responsible. It seems like he has read every post. Thank you for your hard work. Soso is really a good person.

676748500

SOSO is really responsible. It seems like he has read every post. Thank you for your hard work. Soso is really a good person.

雪似梅花

This is a classic question. You can only gain something from things after you have experienced them yourself.

forestmeng

I learned a lot from experience. Thank you.