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PMGD780SN
Dual N-channel
μTrenchMOS
standard level FET
Rev. 02 — 19 April 2010
Product data sheet
1. Product profile
1.1 General description
Dual N-channel enhancement mode field-effect transistor in a small SOT363 (SC-88)
Surface-Mounted Device (SMD) plastic package using TrenchMOS technology.
1.2 Features and benefits
Surface-mounted package
Standard level threshold voltage
Low on-state resistance
Footprint 40 % smaller than SOT23
Fast switching
Dual device
1.3 Applications
Driver circuits
Switching in portable appliances
1.4 Quick reference data
V
DS
≤
60 V
P
tot
≤
0.41 W
I
D
≤
0.49 A
R
DSon
≤
920 mΩ
2. Pinning information
Table 1.
Pin
1
2
3
4
5
6
Pinning - SOT363 (SC-88), simplified outline and symbol
Description
source1 (S1)
gate1 (G1)
drain2 (D2)
source2 (S2)
gate2 (G2)
drain1 (D1)
1
2
3
S
1
G
1
S
2
G
2
Simplified outline
6
5
4
Graphic symbol
D
1
D
2
SOT363 (SC-88)
msd901
NXP Semiconductors
PMGD780SN
Dual N-channel
μTrenchMOS
standard level FET
3. Ordering information
Table 2.
Ordering information
Package
Name
PMGD780SN
SC-88
Description
plastic surface-mounted package; 6 leads
Version
SOT363
Type number
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
[1]
Conditions
25
°C ≤
T
j
≤
150
°C
25
°C ≤
T
j
≤
150
°C;
R
GS
= 20 kΩ
T
sp
= 25
°C;
V
GS
= 10 V;
Figure 2
and
3
T
sp
= 100
°C;
V
GS
= 10 V;
Figure 2
T
sp
= 25
°C;
pulsed; t
p
≤
10
μs;
Figure 3
T
sp
= 25
°C;
Figure 1
[1]
[1]
[1]
Min
-
-
-
-
-
-
-
−55
−55
Max
60
60
±20
0.49
0.31
0.99
0.41
+150
+150
0.34
0.69
Unit
V
V
V
A
A
A
W
°C
°C
A
A
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
Single device conducting.
Source-drain diode
T
sp
= 25
°C
T
sp
= 25
°C;
pulsed; t
p
≤
10
μs
[1]
[1]
-
-
PMGD780SN_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 19 April 2010
2 of 14
NXP Semiconductors
PMGD780SN
Dual N-channel
μTrenchMOS
standard level FET
120
P
der
(%)
80
03aa17
120
I
der
(%)
80
03aa25
40
40
0
0
50
100
150
T
sp
(°C)
200
0
0
50
100
150
T
sp
(°C)
200
P
tot
P
der
=
----------------------
×
100%
-
P
°
tot
(
25 C
)
I
D
I
der
=
------------------
×
100%
-
I
°
D
(
25 C
)
Fig 1.
Normalized total power dissipation as a
function of solder point temperature
Fig 2.
Normalized continuous drain current as a
function of solder point temperature
10
ID
(A)
1
03an22
Limit RDSon = VDS / ID
tp = 10
μ
s
100
μ
s
10-1
1 ms
DC
10 ms
100 ms
10-2
10-3
10-1
1
10
VDS (V)
102
T
sp
= 25
°C;
I
DM
is single pulse; V
GS
= 10 V
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PMGD780SN_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 19 April 2010
3 of 14
NXP Semiconductors
PMGD780SN
Dual N-channel
μTrenchMOS
standard level FET
5. Thermal characteristics
Table 4.
R
th(j-sp)
Thermal characteristics
Conditions
Figure 4
Min
-
Typ
-
Max
300
Unit
K/W
thermal resistance from junction to solder point
Symbol Parameter
103
Zth(j-sp)
(K/W)
δ
= 0.5
102
0.2
0.1
0.05
0.02
10
single pulse
P
03an28
δ
=
tp
T
tp
T
1
10-4
10-3
10-2
10-1
1
t
tp (s)
10
Fig 4.
Transient thermal impedance from junction to solder point as a function of pulse duration
PMGD780SN_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 19 April 2010
4 of 14
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