ICSSSTU32864YHT datasheet, PDF

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ICSSSTU32864YHT: DescriptionD Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, MO-205CC, LFBGA-96; Categorylogic logic; File Size111KB，11 Pages; ManufacturerIDT (Integrated Device Technology)

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ICSSSTU32864YHT Overview

D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, MO-205CC, LFBGA-96

ICSSSTU32864YHT Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	MO-205CC, LFBGA-96
Contacts	96
Reach Compliance Code	compliant
series	SSTU
JESD-30 code	R-PBGA-B96
JESD-609 code	e0
length	13.5 mm
Logic integrated circuit type	D FLIP-FLOP
Number of digits	25
Number of functions	1
Number of terminals	96
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
propagation delay (tpd)	1.85 ns
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	5.5 mm
minfmax	270 MHz

ICSSSTU32864YHT Preview

Integrated

Circuit

Systems, Inc.

ICSSSTU32864

25-Bit Configurable Registered Buffer

Recommended Application:

•

DDR2 Memory Modules

•

Provides complete DDR DIMM logic solution with

ICS97U877

Product Features:

•

25-bit 1:1 or 14-bit 1:2 configurable registered buffer

•

Supports SSTL_18 JEDEC specification on data

inputs and outputs

•

Supports LVCMOS switching levels on CSR# and

RESET# inputs

•

Low voltage operation

= 1.7V to 1.9V

•

Available in 96 BGA package

Pin Configuration

96 Ball BGA

(Top View)

Truth Table

I nputs

RST#

DCS#

X or

Floating

CSR#

X or

Floating

L or H

X or

Floating

L or H

X or

Floating

L or H

CK#

Dn,

DODT,

DCK E

X or

Floating

Outputs

QCS#

QODT,

QCKE

Ball Assignments

DCKE

DODT

CK#

D15

D16

D17

D18

RST#

DCS#

CSR#

D19

D20

D21

D22

D23

D24

D25

REF

GND

REF

GND

QCKE

QODT

QCS#

ZOH

Q10

Q11

Q12

Q13

Q14

Q15

Q16

Q17

Q18

ZOL

Q19

Q20

Q21

Q22

Q23

Q24

Q25

D10

D11

D12

D13

D14

1:1 Register (C0 = 0, C1 = 0)

0727C—04/15/04

ICSSSTU32864

Ball Assignments

DCKE

DODT

CK#

D10

D11

D12

D13

D14

RST#

DCS#

CSR#

REF

GND

REF

GND

QCKEA

Q2A

Q3A

QODTA

Q5A

Q6A

QCSA#

ZOH

Q8A

Q9A

Q10A

Q11A

Q12A

Q13A

Q14A

QCKEB

Q2B

Q3B

QODTB

Q5B

Q6B

QCSB#

ZOL

Q8B

Q9B

Q10B

Q11B

Q12B

Q13B

Q14B

Ball Assignments

CK#

RST#

DCS#

CSR#

REF

GND

REF

GND

Q1A

Q2A

Q3A

Q4A

Q5A

Q6A

QCSA#

ZOH

Q8A

Q9A

Q10A

QODTA

Q12A

Q13A

QCKEA

Q1B

Q2B

Q3B

Q4B

Q5B

Q6B

QCSB#

ZOL

Q8B

Q9B

Q10B

QODTB

Q12B

Q13B

QCKEB

D10

DODT

D12

D13

DCKE

1:2 Register A (C0 = 0, C1 = 1)

General Description

1:2 Register B (C0 = 1, C1 = 1)

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All

outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load.

ICSSSTU32864

operates

from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going low.

The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when

high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).

The device supports low-power standby operation. When the reset input (RST#) is low, the differential input receivers

are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when

RST# is low all registers are reset, and all outputs are forced low. The LVCMOS RST# and Cn inputs must always be

held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied,

RST# must be held in the low state during power up.

In the DDR-II RDIMM application, RST# is specified to be completely asynchronous with respect to CK and CK#.

Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared

and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers.

As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST# until

the input receivers are fully enabled, the design of the

ICSSSTU32864

must ensure that the outputs will remain low,

thus ensuring no glitches on the output.

The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS#

and CSR# inputs are high. If either DCS# or CSR# input is low, the Qn outputs will function normally. The RST input

has priority over the DCS# and CSR# control and will force the outputs low. If the DCS#-control functionality is not

desired, then the CSR# input can be hardwired to ground, in which case, the setup-time requirement for DCS# would

be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC).

0727C—04/15/04

ICSSSTU32864

Ball Assignment

Terminal Name

GND

REF

C0, C1

RST#

CSR#, DCS#

D1 - D25

DODT

DCKE

Q1 - Q25

QCS#

QODT

QCKE

Ground

Power supply voltage

Input reference voltage

Reserved for future use

Positive master clock input

Negative master clock input

Configuration control inputs

Asynchronous reset input - resets registers and disables V

REF

data and

clock differential-input receivers

Description

Electrical

Characteristics

Ground input

1.8V nominal

0.9V nominal

Input

Differential input

LVCMOS inputs

LV C M O S i n p u t

Chip select inputs - disables D1 - D24 outputs switching when both inputs

SSTL_18 input

are high

Data input - clock in on the crossing of the rising edge of CK and the

falling edge of CK#

The outputs of this register bit will not be suspended by the DCS# and

CSR# control

The outputs of this register bit will now be suspended by the DCS# and

CSR# control

Data ouputs that are suspended by the DCS# and CSR# control

Data output that will not be suspended by the DCS# and CSR# control

SSTL_18 input

1.8V CMOS

0727C—04/15/04

ICSSSTU32864

Block Diagram for 1:1 mode (positive logic)

RST#

CK#

REF

DCKE

QCKEA

DODT

QODTA

DCS#

QCSA#

CSR#

Q1B

Q1A

To 21 Other Channels

*Note: Disabled in 1:1 configuration

0727C—04/15/04

ICSSSTU32864

Block Diagram for 1:2 mode (positive logic)

RST#

CK#

REF

DCKE

QCKEA

QCKEB*

DODT

QODTA

QODTB*

DCS#

QCSA#

QCSB#*

CSR#

Q1B

Q1A

To 10 Other Channels

*Note: Disabled in 1:1 configuration

0727C—04/15/04

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ICSSSTU32864YHT Related Products

	ICSSSTU32864YHT	ICSSSTU32864YHLFT
Description	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, MO-205CC, LFBGA-96	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, MO-205CC, LFBGA-96
Is it lead-free?	Contains lead	Lead free
Is it Rohs certified?	incompatible	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	BGA	BGA
package instruction	MO-205CC, LFBGA-96	MO-205CC, LFBGA-96
Contacts	96	96
Reach Compliance Code	compliant	compliant
series	SSTU	SSTU
JESD-30 code	R-PBGA-B96	R-PBGA-B96
JESD-609 code	e0	e1
length	13.5 mm	13.5 mm
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP
Number of digits	25	25
Number of functions	1	1
Number of terminals	96	96
Maximum operating temperature	70 °C	70 °C
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFBGA	LFBGA
Package shape	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	260
propagation delay (tpd)	1.85 ns	1.85 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.5 mm	1.5 mm
Maximum supply voltage (Vsup)	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V
surface mount	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
Trigger type	POSITIVE EDGE	POSITIVE EDGE
width	5.5 mm	5.5 mm
minfmax	270 MHz	270 MHz

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