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DP5Z2MX8PAJY-12B

Description
Flash, 2MX8, 120ns, J LEAD, SLCC-48
Categorystorage    storage   
File Size633KB,25 Pages
ManufacturerTwilight Technology Inc.
Download Datasheet Parametric View All

DP5Z2MX8PAJY-12B Overview

Flash, 2MX8, 120ns, J LEAD, SLCC-48

DP5Z2MX8PAJY-12B Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerTwilight Technology Inc.
Parts packaging codeQMA
package instructionQCCJ, LDCC48,.51X.88
Contacts48
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Maximum access time120 ns
Data pollingYES
JESD-30 codeR-XQMA-J48
memory density16777216 bit
Memory IC TypeFLASH
memory width8
Number of functions1
Number of departments/size32
Number of terminals48
word count2097152 words
character code2000000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize2MX8
Package body materialUNSPECIFIED
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC48,.51X.88
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Programming voltage5 V
Certification statusNot Qualified
ready/busyYES
Filter levelMIL-STD-883
Department size64K
Maximum standby current0.000005 A
Maximum slew rate0.06 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
switch bitYES
typeNOR TYPE
write protectHARDWARE
16 Megabit FLASH EEPROM
DP5Z2MX8PAnY
PRELIMINARY
DESCRIPTION:
The DP5Z2MX8PAnY “SLCC” devices are a revolutionary new memory
subsystem using Dense-Pac Microsystems’ ceramic Stackable Leadless Chip
Carriers (SLCC). Available unleaded, straight leaded, “J” leaded, gullwing
leaded packages, or mounted on a 50-pin PGA co-fired ceramic substrate.
The Device packs 16-Megabits of FLASH EEPROM in an area as small as
0.463 in2 while maintaining a total height as low as 0.171 inches.
The DP5Z2MX8PAnY is a 2 Meg x 8 FLASH EEPROM based memory module.
Each SLCC is hermetically sealed making the module suitable for commercial,
industrial and military applications.
By using SLCCs, the “Stack” family of modules offer a higher board density
of memory than available with conventional through-hole, surface mount or
hybrid techniques.
DP5Z2MX8PAY3
DP5Z2MX8PAH3
FEATURES:
Organization: 2 Meg x 8
Fast Access Times: 70*, 90, 120, 150ns (max.)
* V
DD
= 5.0V
±
5%
Single 5.0 Volt Power Supply
High-Density Symmetrically Blocked Architecture
- 32 Uniform Sectors of 64 Kbytes Each
Extended Cycling Capability
- 100,000 Write/Erase Cycles per Sector
Automated Erase and Program Cycles
- Command User Interface
- Status Register
DP5Z2MX8PAJ3
SRAM-Compatible Write Interface
Hardware Data Protection Feature
Packages Available:
DP5Z2MX8PAY
DP5Z2MX8PAIY
DP5Z2MX8PAHY
DP5Z2MX8PAJY
DP5Z2MX8PAA3
- Erase / Write Lockout during Power Transitions
48 - Pin SLCC
48 - Pin Straight Leaded SLCC
48 - Pin Gullwing Leaded SLCC
48 - Pin J Leaded SLCC
50 - Pin PGA Dense-SLCC
DP5Z2MX8PAA3
DP5Z2MX8PAI3
30A161-A1
Rev. A
This document contains information on a product under consideration for
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right
to
c
hange or discontinue information on this product without prior notice.
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