White Electronic Designs
W3EG7264S-AD4
-BD4
PRELIMINARY*
512MB – 2x32Mx72 DDR ECC SDRAM UNBUFFERED w/PLL
FEATURES
Double-data-rate architecture
DDR200, DDR266 DDR333
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Dual Rank
Power supply: 2.5V ± 0.2V
200 pin SO-DIMM package
• Package height options:
AD4: 35.05 mm (1.38”)
BD4: 31.75 mm (1.25”)
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
* This product is under development, is not qualified or characterized and is subject to
change without notice.
DESCRIPTION
The W3EG7264S is a 2x32Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of nine 64Mx8 DDR
SDRAMs stacked in 54 pin TSOP packages mounted on
a 200 pin FR4 substrate. This module is structured as 2
Ranks of 64Mx72 DDR SDRAM.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
OPERATING FREQUENCIES
DDR333@CL=2.5
Clock Speed
CL-t
RCD
-t
RP
166MHz
2.5-3-3
DDR266@CL=2
133MHz
2-2-2
DDR266@CL=2.5
133MHz
2.5-3-3
DDR200@CL=2
100MHz
2-2-2
January 2005
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN CONFIGURATION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Symbol
V
REF
V
REF
V
SS
V
SS
DQ0
DQ4
DQ1
DQ5
V
CC
V
CC
DQS0
DQM0
DQ2
DQ6
V
SS
V
SS
DQ3
DQ7
DQ8
DQ12
V
CC
V
CC
DQ9
DQ13
DQS1
DQM1
V
SS
V
SS
DQ10
DQ14
DQ11
DQ15
V
CC
V
CC
CK0
V
CC
CK0#
V
SS
V
SS
V
SS
DQ16
DQ20
DQ17
DQ21
V
CC
V
CC
DQS2
DQM2
DQ18
DQ22
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
V
SS
V
SS
DQ19
DQ23
DQ24
DQ28
V
CC
V
CC
DQ25
DQ29
DQS3
DQM3
V
SS
V
SS
DQ26
DQ30
DQ27
DQ31
V
CC
V
CC
CB0
CB4
CB1
CB5
V
SS
V
SS
DQS8
DQM8
CB2
CB6
V
CC
V
CC
CB3
CB7
NC
NC
V
SS
V
SS
CK2*
V
SS
CK2#*
V
CC
V
CC
V
CC
CKE1
CKE0
NC
NC
A12
A11
Pin
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
A9
A8
V
SS
V
SS
A7
A6
A5
A4
A3
A2
A1
A0
V
CC
V
CC
A10/AP
BA1
BA0
RAS#
WE#
CAS#
CS0#
CS1#
NC
NC
V
SS
V
SS
DQ32
DQ36
DQ33
DQ37
V
CC
V
CC
DQS4
DQM4
DQ34
DQ38
V
SS
V
SS
DQ35
DQ39
DQ40
DQ44
V
CC
V
CC
DQ41
DQ45
DQS5
DQM5
V
SS
V
SS
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Symbol
DQ42
DQ46
DQ43
DQ47
V
CC
V
CC
V
CC
CK1#*
V
SS
CK1*
V
SS
V
SS
DQ48
DQ52
DQ49
DQ53
V
CC
V
CC
DQS6
DQM6
DQ50
DQ54
V
SS
V
SS
DQ51
DQ55
DQ56
DQ60
V
CC
V
CC
DQ57
DQ61
DQS7
DQM7
V
SS
V
SS
DQ58
DQ62
DQ59
DQ63
V
CC
V
CC
SDA
SA0
SCL
SA1
V
CCSPD
SA2
V
CCID
NC
A0 – A12
BA0-BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
CK0
CK0#
CKE0-CKE1
CS0#-CS1#
RAS#
CAS#
WE#
DQM0-DQM8
V
CC
V
SS
V
REF
V
CCSPD
SDA
SCL
SA0-SA2
V
CCID
NC
W3EG7264S-AD4
-BD4
PRELIMINARY
PIN NAMES
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Check bits
Data Strobe Input/Output
Clock Input
Clock input
Clock Enable input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
Data-In Mask
Power Supply (2.5V)
Ground
Power Supply for Reference
Serial EEPROM Power Supply (2.3V to 3.6V)
Serial data I/O
Serial clock
Address in EEPROM
V
CC
Identification Flag
No Connect
* Not Used
January 2005
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
W3EG7264S-AD4
-BD4
PRELIMINARY
CS1#
CS0#
DQS0
DQM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DQM8
CS#
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
CK0
120Ω
CK0A
V
CC
DDR SDRAM
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CS#
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQM7
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
CS#
CS#
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQM6
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
CS#
CS#
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQM5
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
CS#
DQS4
DQM4
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
CS#
CS#
PLL
CK0#
CK0A#
FEEDBACK
RAS#
CAS#
BA0-BA1
WE#
A0-A12
CKE0
CKE1
RAS: DDR SDRAMs
CAS: DDR SDRAMs
BA0-BA1: DDR SDRAMs
WE: DDR SDRAMs
A0-A12: DDR SDRAMs
CKE0: DDR SDRAMs
CKE1: DDR SDRAMs
V
CC
GND
DDR SDRAM
DDR SDRAM
SCL
A0
SA0
A1
SA1
A2
SA2
SERIAL PD
SDA
NOTE: All datalines are terminated through a 22 ohm series resistor.
January 2005
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Current
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
W3EG7264S-AD4
-BD4
PRELIMINARY
Symbol
V
IN
, V
OUT
V
CC
, V
CCQ
T
STG
P
D
I
OS
Value
– 0.5 ~ 3.6
–1.0 ~ 3.6
– 55 ~ +150
9
50
Units
V
V
°C
W
mA
0°C
≤
T
A
≤
70°C,
V
CC
= 2.5V ± 0.2V
Parameter
Supply Voltage
Supply Voltage
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Symbol
V
CC
V
CCQ
V
REF
V
TT
V
IH
V
IL
V
OH
V
OL
Min
2.3
2.3
1.15
1.15
V
REF
+ 0.15
– 0.3
V
TT
+ 0.76
—
Max
2.7
2.7
1.35
1.35
V
CCQ
+ 0.3
V
REF
– 0.15
—
V
TT
– 0.76
Unit
V
V
V
V
V
V
V
V
DC CHARACTERISTICS
CAPACITANCE
T
A
= 25°C, f = 1MHz, V
CC
= 2.5V
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0,CKE1)
Input Capacitance (CK0,CK0#)
Input Capacitance (CS0#,CS1#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output Capacitance (DQ0-DQ63)(DQS)
Data input/output Capacitance (CB0-CB7)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
IN7
C
OUT
C
OUT
Max
56
56
29
5.5
29
13
56
13
13
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
January 2005
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
I
DD
SPECIFICATIONS AND TEST CONDITIONS
W3EG7264S-AD4
-BD4
PRELIMINARY
Recommended operating conditions, 0°C
≤
T
A
≤
70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V
DDR333@CL=2.5 DDR266@CL=2, 2.5
Parameter
Operating Current
Symbol Conditions
I
DD0
One device bank; Active - Precharge;
(MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address
and control inputs changing once every
two cycles. T
RC
=T
RC
(MIN); T
CK
=T
CK
One device bank; Active-
Read-Precharge; Burst = 2;
T
RC
=T
RC
(MIN);T
CK
=T
CK
(MIN); Iout
= 0mA; Address and control inputs
changing once per clock cycle.
All device banks idle; Power-down
mode; T
CK
=T
CK
(MIN); CKE=(low)
CS# = High; All device banks idle;
T
CK
=T
CK
(MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. V
IN
= V
REF
for DQ, DQS
and DM.
One device bank active; Power-down
mode; T
CK
(MIN); CKE=(low)
CS# = High; CKE = High; One
device bank; Active-Precharge;
T
RC
=T
RAS
(MAX); T
CK
=T
CK
(MIN); DQ,
DM and DQS inputs changing twice per
clock cycle; Address and other control
inputs changing once per clock cycle.
Burst = 2; Reads; Continous burst; One
device bank active;Address andcontrol
inputs changing once per clock cycle;
T
CK
=T
CK
(MIN); I
OUT
= 0mA.
Burst = 2; Writes; Continous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
T
CK
=T
CK
(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
T
RC
=T
RC
(MIN)
CKE ≤ 0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with T
RC
=T
RC
(MIN);
T
CK
=T
CK
(MIN); Address and control
inputs change only during Active Read
or Write commands
Max
2205
Max
2025
DDR200@CL=2
Max
2025
Units
mA
Operating Current
I
DD1
2610
2340
2340
mA
Precharge Power-Down
Standby Current
Idle Standby Current
I
DD2P
I
DD2F
72
900
72
810
72
810
mA
mA
Active Power-Down
Standby Current
Active Standby Current
I
DD3P
I
DD3N
540
1080
450
900
450
900
mA
mA
Operating Current
I
DD4R
2655
2250
2250
mA
Operating Current
I
DD4W
2655
2250
2250
mA
Auto Refresh Current
Self Refresh Current
Operating Current
I
DD5
I
DD6
I
DD7A
3375
72
4770
3015
72
4050
3015
72
4050
mA
mA
mA
January 2005
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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