ES_LPC435x/3x/2x/1x
Errata sheet LPC435x/3x/2x/1x
Rev. 2 — 20 October 2012
Errata sheet
Document information
Info
Keywords
Content
LPC4357FET256; LPC4357JET256; LPC4357JBD208; LPC4353FET256;
LPC4353JET256; LPC4353JBD208; LPC4337FET256; LPC4337JET256;
LPC4337JBD144; LPC4337JET100; LPC4333FET256; LPC4333JET256;
LPC4333JBD144; LPC4333JET100; LPC4327JBD144; LPC4327JET100;
LPC4325JBD144; LPC4325JET100; LPC4323JBD144; LPC4323JET100;
LPC4322JBD144; LPC4322JET100; LPC4317JBD144; LPC4317JET100;
LPC4315JBD144; LPC4315JET100; LPC4313JBD144; LPC4313JET100;
LPC4312JBD144; LPC4312JET100 errata
This errata sheet describes both the known functional problems and any
deviations from the electrical specifications known at the release date of
this document.
Each deviation is assigned a number and its history is tracked in a table.
Abstract
NXP Semiconductors
ES_LPC435x/3x/2x/1x
Errata sheet LPC435x/3x/2x/1x
Revision history
Rev
2
Date
20121020
Description
1.1
20120808
1
20120717
•
•
•
•
•
•
•
•
Added PWR.1, IRC.1.
Removed AES.1, ETM.1, RGU.1, SPIFI.1; documented in user manual.
Updated EEPROM.1, C_CAN.1, IBAT.1.
Added LPC432x and LPC431x parts.
Document title changed from ES_LPC4357_53_37_33 to ES_LPC435X_3X_2X_1X.
Added RGU.1 and EEPROM.1.
Corrected C_CAN0/C_CAN1 peripheral assignment.
Initial version.
Contact information
For more information, please visit:
http://www.nxp.com
For sales office addresses, please send an email to:
salesaddresses@nxp.com
ES_LPC435X_3X_2X_1X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Errata sheet
Rev. 2 — 20 October 2012
2 of 11
NXP Semiconductors
ES_LPC435x/3x/2x/1x
Errata sheet LPC435x/3x/2x/1x
1. Product identification
The LPC435x/3x/2x/1x devices (hereafter referred to as ‘LPC43xx’) typically have the
following top-side marking:
LPC43xxxxxxxx
xxxxxxxx
xxxYYWWxR[x]
The last/second to last letter in the last line (field ‘R’) will identify the device revision. This
Errata Sheet covers the following revisions of the LPC43xx:
Table 1.
‘-’
Device revision table
Revision description
Initial device revision
Revision identifier (R)
Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the
device was manufactured during that year.
2. Errata overview
Table 2.
Functional
problems
C_CAN.1
EEPROM.1
MCPWM.1
PMC.1
Functional problems table
Short description
Writes to CAN registers write through to other
peripherals
Limited EEPROM retention and endurance
MCPWM abort pin not functional
PMC.x power management controller fails to wake up
from deep sleep, power down, or deep power down
AC/DC deviations table
Short description
VBAT supply current higher than expected
IRC frequency variation higher than expected
Higher than expected IO current
Errata notes table
Short description
n/a
Revision identifier
n/a
Detailed description
n/a
Product version(s)
‘-’
‘-’
‘-’
Detailed description
Section 4.1
Section 4.2
Section 4.3
Revision identifier
‘-’
‘-’ (with date code
<1242)
‘-’
‘-’
Detailed description
Section 3.1
Section 3.2
Section 3.3
Section 3.4
Table 3.
AC/DC
deviations
IBAT.1
IRC.1
PWR.1
Table 4.
n/a
Errata notes
ES_LPC435X_3X_2X_1X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Errata sheet
Rev. 2 — 20 October 2012
3 of 11
NXP Semiconductors
ES_LPC435x/3x/2x/1x
Errata sheet LPC435x/3x/2x/1x
3. Functional problems detail
3.1 C_CAN.1: Writes to CAN registers write through to other peripherals
Introduction:
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a very high level of security.
Problem:
On the LPC43xx, there is an issue with the C_CAN controller AHB bus address decoding
that applies to both C_CAN controllers. It affects the C_CAN controllers when peripherals
on the same bus are used. Writes to the ADC, DAC, I2C, and I2S peripherals can update
registers in the C_CAN controller. Specifically, writes to I2C0, MCPWM, and I2S can affect
C_CAN1. Writes to I2C1, DAC, ADC0, and ADC1 can affect C_CAN0. The spurious
C_CAN controller writes will occur at the address offset written to the other peripherals on
the same bus. For example, a write to ADC0 CR register which is at offset 0 in the ADC,
will result in the same value being written to the C_CAN0 CNTL register which is at offset
0 in the C_CAN controller. Writes to the C_CAN controller will not affect other peripherals.
Work-around:
Workarounds include: Using a different C_CAN peripheral. Peripherals I2C1, DAC, ADC0,
and ADC1 can be used at the same time as C_CAN1 is active without any interference.
The I2C0, MCPWM, and I2S peripherals can be used at the same time as C_CAN0 is
active without any interference. Another workaround is to gate the register clock to the
CAN peripheral in the CCU. This will prevent any writes to other peripherals from taking
effect in the CAN peripheral. However, gating the CAN clock will prevent the CAN
peripheral from operating and transmitting or receiving messages. This workaround is
most useful if your application is modal and can switch between different modes such as
an I2S mode and a CAN mode. Another workaround is to avoid writes to the peripherals
while CAN is active. For example, the ADC could be configured to sample continuously or
when triggered by a timer, before the CAN is configured. Afterwards, C_CAN0 can be
used since the ADC will operate without requiring additional writes.
ES_LPC435X_3X_2X_1X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Errata sheet
Rev. 2 — 20 October 2012
4 of 11
NXP Semiconductors
ES_LPC435x/3x/2x/1x
Errata sheet LPC435x/3x/2x/1x
3.2 EEPROM.1: Limited EEPROM retention and endurance
Introduction:
The LPC43xx contain a 16384 byte EEPROM memory with endurance of > 100 k erase /
program cycles.
Problem:
On the LPC43xx LBGA parts with date code <1242, EEPROM endurance and retention
may be less than specified. All newer parts will have fully tested EEPROMs.
Work-around:
Using longer EEPROM write times will increase retention.
ES_LPC435X_3X_2X_1X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Errata sheet
Rev. 2 — 20 October 2012
5 of 11
MCU
京公网安备 11010802033920号
EEWORLD
