LPC4317JET100 datasheet, PDF - EEWORLD Datasheet

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LPC4317JET100: DescriptionErrata sheet LPC435x/3x/2x/1x; CategoryThe embedded processor and controller Microcontrollers and processors; File Size67KB，11 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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LPC4317JET100 Overview

Errata sheet LPC435x/3x/2x/1x

LPC4317JET100 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	NXP
package instruction	9 X 9 MM, 0.70 MM HEIGHT, PLASTIC, SOT926-1, TFBGA-100
Reach Compliance Code	compli
Has ADC	YES
Address bus width
bit size	32
maximum clock frequency	25 MHz
DAC channel	YES
DMA channel	YES
External data bus width
JESD-30 code	S-PBGA-B100
length	9 mm
Humidity sensitivity level	3
Number of I/O lines	49
Number of terminals	100
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
PWM channel	NO
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
ROM programmability	FLASH
Maximum seat height	1.2 mm
speed	204 MHz
Maximum supply voltage	3.6 V
Minimum supply voltage	2.2 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	9 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

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ES_LPC435x/3x/2x/1x

Errata sheet LPC435x/3x/2x/1x

Rev. 2 — 20 October 2012

Errata sheet

Document information

Info

Keywords

Content

LPC4357FET256; LPC4357JET256; LPC4357JBD208; LPC4353FET256;

LPC4353JET256; LPC4353JBD208; LPC4337FET256; LPC4337JET256;

LPC4337JBD144; LPC4337JET100; LPC4333FET256; LPC4333JET256;

LPC4333JBD144; LPC4333JET100; LPC4327JBD144; LPC4327JET100;

LPC4325JBD144; LPC4325JET100; LPC4323JBD144; LPC4323JET100;

LPC4322JBD144; LPC4322JET100; LPC4317JBD144; LPC4317JET100;

LPC4315JBD144; LPC4315JET100; LPC4313JBD144; LPC4313JET100;

LPC4312JBD144; LPC4312JET100 errata

This errata sheet describes both the known functional problems and any

deviations from the electrical specifications known at the release date of

this document.

Each deviation is assigned a number and its history is tracked in a table.

Abstract

NXP Semiconductors

ES_LPC435x/3x/2x/1x

Errata sheet LPC435x/3x/2x/1x

3. Functional problems detail

3.1 C_CAN.1: Writes to CAN registers write through to other peripherals

Introduction:

Controller Area Network (CAN) is the definition of a high performance communication

protocol for serial data communication. The C_CAN controller is designed to provide a full

implementation of the CAN protocol according to the CAN Specification Version 2.0B. The

C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by

supporting distributed real-time control with a very high level of security.

Problem:

On the LPC43xx, there is an issue with the C_CAN controller AHB bus address decoding

that applies to both C_CAN controllers. It affects the C_CAN controllers when peripherals

on the same bus are used. Writes to the ADC, DAC, I2C, and I2S peripherals can update

registers in the C_CAN controller. Specifically, writes to I2C0, MCPWM, and I2S can affect

C_CAN1. Writes to I2C1, DAC, ADC0, and ADC1 can affect C_CAN0. The spurious

C_CAN controller writes will occur at the address offset written to the other peripherals on

the same bus. For example, a write to ADC0 CR register which is at offset 0 in the ADC,

will result in the same value being written to the C_CAN0 CNTL register which is at offset

0 in the C_CAN controller. Writes to the C_CAN controller will not affect other peripherals.

Work-around:

Workarounds include: Using a different C_CAN peripheral. Peripherals I2C1, DAC, ADC0,

and ADC1 can be used at the same time as C_CAN1 is active without any interference.

The I2C0, MCPWM, and I2S peripherals can be used at the same time as C_CAN0 is

active without any interference. Another workaround is to gate the register clock to the

CAN peripheral in the CCU. This will prevent any writes to other peripherals from taking

effect in the CAN peripheral. However, gating the CAN clock will prevent the CAN

peripheral from operating and transmitting or receiving messages. This workaround is

most useful if your application is modal and can switch between different modes such as

an I2S mode and a CAN mode. Another workaround is to avoid writes to the peripherals

while CAN is active. For example, the ADC could be configured to sample continuously or

when triggered by a timer, before the CAN is configured. Afterwards, C_CAN0 can be

used since the ADC will operate without requiring additional writes.

ES_LPC435X_3X_2X_1X

All information provided in this document is subject to legal disclaimers.

Errata sheet

Rev. 2 — 20 October 2012

4 of 11

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