Features
•
•
•
•
•
•
•
10-bit Resolution
1.5 Gsps Sampling Rate
Selectable 1:2 or 1:4 Demultiplexed Output
500 mVpp Differential 100Ω or Single-ended 50Ω Analog Input
100Ω Differential or Single-ended 50Ω Clock Input
LVDS Output Compatibility
Functions:
– ADC Gain Adjust
– Sampling Delay Adjust
– 1:4 Demultiplexed Simultaneous or Staggered Digital Outputs
– Data Ready Output with Asynchronous Reset
– Out-of-range Output Bit (11th Bit)
•
Power Consumption: 6.5W
•
Power Supplies: -5V, -2.2V, 3.3V and V
PLUSD
Output Power Supply
•
Package
– Cavity Down EBGA 317 (Enhanced Ball Grid Array)
– 25 × 35 mm Overall Dimensions
10-bit
1.5 Gsps ADC
With
1:4 DMUX
AT84AS003
Performances
• 3 GHz Full-power Analog Input Bandwidth
• - 0.5 dB Gain Flatness from DC up to 1.5 GHz
• Single-tone Performance at Fs = 1.5 Gsps, Full First Nyquist Zone
– ENOB = 8.0 Bits, F
IN
= 750 MHz
– SNR = 52 dBc, SFDR = - 58 dBc, F
IN
= 750 MHz
• Dual-tone Performance (IMD3) at Fs = 1.5 Gsps (- 7 dBF
S
Each Tone)
– Fin1 = 695 MHz, Fin2 = 705 MHz: IMD3 = - 60 dBF
S
Screening
• Temperature Range:
– T
amb
> 0°C; T
J
< 90°C (Commercial
C
Grade)
– T
amb
> - 40°C; T
J
< 110°C (Industrial
V
Grade)
Applications
• Direct RF Down Conversion
• Broadband Digital Receivers
• Test Instrumentation
• High Speed Data Acquisition
• High Energy Physics
5403B–BDC–02/06
1. Description
The AT84AS003 combines a 10-bit 1.5 Gsps analog-to-digital converter with a 1:4 DMUX,
designed for accurate digitization of broadband signals. It features 8.0 Effective Number of Bits
(ENOB) and - 58 dBc Spurious Free Dynamic Range (SFDR) at 1.5 Gsps over the full first
Nyquist zone.
The 1:4 demultiplexed digital outputs are LVDS logic compatible, allowing easy interfacing with
standard FPGAs or DSPs. The AT84AS003 operates at up to 1.5 Gsps. The AT84AS003 comes
in a 25 × 35 mm EBGA 317 package. This package has the same TCE as FR4 boards, offering
excellent reliability when submitted to large thermal shocks.
2. Block Diagram
Figure 2-1.
Block Diagram
BIST
ASYNRST
PGEB
DRRB
SDA
2
CLK/CLKN
SDA
20
2
20
Port A
AOR/AORN
Port B
BOR/BORN
Port C
COR/CORN
Port D
DOR/DORN
DR/DRN
LVDS Buffers
Logic Block
Quantizer
2
20
2
20
2
2
VIN
S/H
VINN
Demultiplexer
1:2 or 1:4
GA
B/GB
SLEEP
STAGG
RS
DRTYPE
2
AT84AS003
5403B–BDC–02/06
AT84AS003
3. Functional Description
The AT84AS003 is a 10-bit 1.5 Gsps ADC combined with a 1:4 demultiplexer (DMUX) allowing
to lower the 11 bit output Data stream (10-bit data and one Out of Range bit) by a selectable fac-
tor of 4 or 2. The ADC works in fully differential mode from analog input up to digital outputs.
The ADC should be 50Ω reverse terminated, as close as possible to the EBGA package input
pin (1 mm maximum). The ADC clock input is on-chip 100Ω differentially terminated. The output
clock and the output data are LVDS logic compatible, and should be 100Ω differentially
terminated.
The AT84AS003 ADC features two asynchronous resets:
– -DRRB, which ensures that the first digitized data corresponds to the first
acquisition.
– ASYNCRST, which ensures that the first digitized data will be output on port A of the
DMUX.
The ADC gain can be tuned in to unity gain by the means of the GA analog control input. A Sam-
pling Delay Adjust function (SDA analog control input, activated via the SDAEN signal) may be
used to fine-tune the ADC aperture delay by ± 120 ps around its center value. The SDA function
may be of interest for interleaving multiple ADCs.The control pin B/GB is provided to select
either a Binary or Gray data output format.
A tunable delay cell (controlled via CLKDACTRL) is integrated between the ADC and the DMUX
on the clock path to fine tune the data vs. clock alignment at the interface between the ADC and
the DMUX. This delay can be tuned from - 275 to 275 ps around default center value, featuring a
550 ps typical delay tuning range. An extra standalone delay cell is also provided, (controlled via
DACTRL analog control input and activated via DAEN). The tuning range is typically 550 ps.
A pattern generator (PGEB) is integrated in the ADC part for debug or acquisition setup . Simi-
larly, a Built-in Self Test (BIST) is provided for quick debug of the DMUX part. The output
demultiplexing 1:4 or 1:2 ratio can be selected by the means of RS digital control input.
Two modes for the output clock (via DRTYPE) can be selected:
• DR mode: only the output clock rising edge is active, the output clock rate is the same as the
output data rate
• DR/2 mode: both the output clock rising and falling edges are active, the output clock rate is
half the output data rate
The data outputs are available at the output of the AT84AS003 in two different modes:
• Staggered: even and odd bits come out with half a data period delay
• Simultaneous: even and odd bits come out at the same time
A power reduction mode (SLEEP control input) is provided to reduce the DMUX power
consumption.
The ADC junction temperature monitoring is made possible through the DIODE input by sensing
the voltage drop across 1 diode implemented on the ADC close to chip hot point.
The AT84AS003 is delivered in an Enhanced Ball Grid Array (EBGA), very suitable for applica-
tions subjected to large thermal variations (thanks to its TCE which is similar to FR4 material
TCE).
3
5403B–BDC–02/06
Table 3-1.
Name
V
CCA
V
CCD
V
EE
V
PLUSD
V
MINUSD
AGND
DGND
CLK, CLKN
VIN, VINN
DRRB
ASYNCRST
DR/DRN
A0…A9
A0N…A9N
AOR/DRAN,
AORN/DRA
B0…B9
B0N…B9N
BOR/DRBN,
BORN/DRB
C0…C9
C0N…C9N
COR/DRCN,
CORN/DRC
D0…D9
D0N…D9N
DOR/DRDN,
DORN/DRD
RS
CLKDACTRL
DACTRL
DAEN
Functions Description
Function
Analog 3.3V power supply
Digital 3.3 V power supply
Analog - 5V power supply
2
VCCA VEE VMINUSD VCCDVPLUSD
3.3V -5V -2.2V
3.3V 2.5V
20
[A0…A9]
[A0N…A9N]
2 AOR/DRAN,
AORN/DRA
20 [B0…B9]
[B0N…B9N]
2 BOR/DRBN,
BORN/DRB
20 [C0…C9]
[C0N…C9N]
2 COR/DRCN,
CORN/DRC
20 [D0…D9]
2 [D0N…D9N]
DOR/DRDN,
DORN/DRD
2
DR, DRN
2
DAO, DAON
DIODE ADC
Output 2.5 V power supply
Output - 2.2V power supply
Analog ground
Digital ground
Input clock signals
Analog input data
ADC reset
DMUX asynchronous reset
Output clock signals
Output data port A
Additional output bit port A
or output clock in staggered mode for
port A
Output data port B
VIN, VINN
CLK, CLKN
DRRB
ASYNCRST
SDAEN
SDA
GA
PG
EB
B/GB
2
AT84AS003
2
DACTRL, CLKDACTRL
2
DAI, DAIN
SLEEP
STAGG
CLKTYPE
RS
DAEN
BIST
DRTYPE
AGND
DGND
Name
DAI, DAIN
DAO, DAON
GA
SDAEN
Function
Input signals for standalone delay cell
Output signals for standalone delay
cell
ADC gain adjust
ADC SDA enable
ADC sampling delay adjust
ADC pattern generator
Binary or gray output code selection
Sleep mode selection signal
Staggered mode selection for Data
outputs
Input clock type selection signal (to be
connected to V
CCD
or left floating)
Output clock type selection signal
Built-in Self Test
Diode for die junction temperature
monitoring (ADC)
Additional output bit port B or output
clock in staggered mode for port B
Output data port C
SDA
Additional output bit port C
or Output clock in staggered mode for
Port C
Output data port D
SLEEP
Additional output bit port D or output
clock in staggered mode for port D
DMUX ratio selection signal
Control signal for clock delay cell
Control signal for standalone delay cell
Enable signal for standalone delay cell
STAGG
CLKTYPE
DRTYPE
BIST
DIODE ADC
PGEB
B/GB
4
AT84AS003
5403B–BDC–02/06
AT84AS003
4. Specifications
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings
Symbol
V
CCA
V
CCD
V
EE
V
PLUSD
V
MINUSD
V
PLUSD
- V
MINUSD
V
IN
or V
INN
V
IN
or V
INN
V
CLK
or V
CLKN
V
CLK
- V
CLKN
GA, SDA
SDAEN, B/GB, PGEB, DECB
DRRB
RS, CLKTYPE, DRTYPE, SLEEP,
STAGG, BIST, DAEN
ASYNCRST
DAI, DAIN
CLKDACTRL, DACTRL
DIODE ADC
DIODE ADC
T
J
Value
GND to 6
GND to 3.6
GND to - 5.5
GND to 3
GND to - 3
5
- 1.5 to 1.5
- 1.5 to 1.5
- 1 to 1
- 1 to 1
- 1 to 0.8
- 5 to 0.8
-0.3 to V
CCA
+ 0.3
- 0.3 to V
CCD
+ 0.3
- 0.3 to V
CCD
+ 0.3
- 0.3 to V
CCD
+ 0.3
- 0.3 to V
CCD
+ 0.3
700
1
135
V
V
mV
mA
°C
V
Vpp
V
V
V
V
Unit
V
V
V
V
V
V
V
Table 4-1.
Parameter
Analog positive supply voltage
Digital positive supply voltage
Analog negative supply voltage
Digital positive supply voltage
Digital negative supply voltage
Maximum difference between
V
PLUSD
and V
MINUSD
Analog input voltages
Maximum difference between
V
IN
and V
INN
Clock input voltage
Maximum difference between
V
CLK
and V
CLKN
Control input voltage
Digital input voltage
ADC reset voltage
DMUX function input voltage
DMUX asynchronous reset
DMUX input voltage
DMUX control voltage
Maximum input voltage on DIODE
Maximum input current on DIODE
Junction temperature
Notes:
1. Absolute maximum ratings are short term limiting values (referenced to GND = 0 V), to be applied individually, while other
parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability.
2. All integrated circuits have to be handled with appropriate care to avoid damage due to ESD. Damage caused by inappropri-
ate handling or storage could range from performance degradation to complete failure.
5
5403B–BDC–02/06
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