TSA5526M datasheet, PDF - EEWORLD Datasheet

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TSA5526M: DescriptionIC PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16, 4.40 MM, PLASTIC, SSOP-16, PLL or Frequency Synthesis Circuit; CategoryAnalog mixed-signal IC The signal circuit; File Size200KB，28 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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TSA5526M Overview

IC PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16, 4.40 MM, PLASTIC, SSOP-16, PLL or Frequency Synthesis Circuit

TSA5526M Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	SOIC
package instruction	LSSOP,
Contacts	16
Reach Compliance Code	unknown
Other features	ALSO REQUIRES 4.5V TO 13.5V SUPPLY
Analog Integrated Circuits - Other Types	PLL FREQUENCY SYNTHESIZER
JESD-30 code	R-PDSO-G16
JESD-609 code	e4
length	5.2 mm
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-20 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Temperature level	OTHER
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	4.4 mm

TSA5526M Preview

INTEGRATED CIRCUITS

DATA SHEET

TSA5526; TSA5527

1.3 GHz universal bus-controlled

TV synthesizers

Product speciﬁcation

Supersedes data of 1995 Mar 22

File under Integrated Circuits, IC02

1996 Sep 24

Philips Semiconductors

Product speciﬁcation

1.3 GHz universal bus-controlled

TV synthesizers

FEATURES

•

Complete 1.3 GHz single chip system

•

Four PNP band switch buffers (40 mA)

•

33 V output tuning voltage

•

In-lock detector

•

5-step ADC

•

15-bit programmable divider

•

Programmable reference divider ratio

(512, 640 or 1024)

•

Programmable charge-pump current (60 or 280

µA)

•

Programmable automatic charge-pump current switch

•

Varicap drive disable

•

Universal bus protocol I

C-bus or 3-wire bus:

– bus protocol for 18 or 19 bits transmission

(3-wire bus)

– extra protocol for 27 bits for test and features

(3-wire bus)

– address plus 4 data bytes transmission (I

C-bus write

mode)

– address plus 1 status byte transmission (I

C-bus

read mode)

– three independent I

C-bus addresses

•

Low power and low radiation.

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME

TSA5526M

TSA5526T

TSA5527M

TSA5527T

TSA5526AM

TSA5526AT

TSA5527AM

TSA5527AT

SSOP16

SO16

SSOP16

SO16

SSOP16

SO16

SSOP16

SO16

DESCRIPTION

APPLICATIONS

TSA5526; TSA5527

•

TV tuners and front ends

•

VCR tuners.

VERSION

SOT369-1

SOT109-1

SOT369-1

SOT109-1

SOT369-1

SOT109-1

SOT369-1

SOT109-1

plastic shrink small outline package; 16 leads; body width 4.4 mm

plastic small outline package; 16 leads; body width 3.9 mm

plastic shrink small outline package; 16 leads; body width 4.4 mm

plastic small outline package; 16 leads; body width 3.9 mm

plastic shrink small outline package; 16 leads; body width 4.4 mm

plastic small outline package; 16 leads; body width 3.9 mm

plastic shrink small outline package; 16 leads; body width 4.4 mm

plastic small outline package; 16 leads; body width 3.9 mm

1996 Sep 24

Philips Semiconductors

Product speciﬁcation

1.3 GHz universal bus-controlled

TV synthesizers

QUICK REFERENCE DATA

SYMBOL

CC1

CC2

CC1

CC2

i(RF)

PARAMETER

supply voltage (+5 V)

band switch supply voltage (12 V)

supply current

band switch supply current

RF input frequency

RF input voltage

= 80 to 150 MHz

= 150 to 1000 MHz

= 1000 to 1300 MHz

xtal

o(PNP)

tot

stg

amb

Notes

1. One band switch buffer ON, I

= 40 mA.

crystal oscillator input frequency

PNP band switch buffers output

current

total power dissipation

storage temperature

operating ambient temperature

note 2

note 3

note 1

CONDITIONS

MIN.

4.5

CC1

−

−25

−28

−15

3.2

−

−40

−20

TSA5526; TSA5527

TYP.

−

4.0

−

250

−

MAX.

5.5

13.5

1300

4.48

400

+150

+85

UNIT

MHz

dBm

MHz

°C

2. One band switch buffer ON, I

= 40 mA; two buffers ON, maximum sum of I

= 50 mA.

3. The power dissipation is calculated as follows:

CC1

CC2

× (

CC2

–

)

(

satPNP

)

(

V33

⁄

) ⁄

27 kΩ.

1996 Sep 24

Philips Semiconductors

Product speciﬁcation

1.3 GHz universal bus-controlled

TV synthesizers

GENERAL DESCRIPTION

The device is a single-chip PLL frequency synthesizer

designed for TV and VCR tuning systems. The circuit

consists of a divide-by-eight prescaler with its own

preamplifier, a 15-bit programmable divider, a crystal

oscillator and its programmable reference divider and a

phase/frequency detector combined with a charge-pump

which drives the tuning amplifier and the 33 V output.

Four high-current PNP band switch buffers are provided

for band switching. Two PNP buffers can be switched on

simultaneously. The sum of the collector currents is limited

to 50 mA.

Depending on the reference divider ratio (512, 640 or

1024), the phase comparator operates at 3.90625 kHz,

6.25 kHz or 7.8125 kHz using a 4 MHz crystal.

The device can be controlled in accordance with the

C-bus format or the 3-wire bus format depending on the

voltage applied to the SW input (see Table 2). In the 3-wire

bus mode (SW = HIGH) pin 12 is the LOCK output.

The lock output is LOW when the PLL loop is locked. In the

C-bus mode (SW = LOW) the LOCK detector bit FL is set

to logic 1 when the loop is locked and is read on the SDA

line (status byte) during a read operation. The ADC input

is available on pin 12 for AFC control in the I

C-bus mode

only. The ADC code is read during a read operation on the

C-bus. In the test mode pin 12 is used as a test output for

ref

and

⁄

div

in the I

C-bus mode and the 3-wire bus mode

(see Table 6).

When the automatic charge-pump current switch mode is

activated, depending on the device given in Table 6, and

when the loop is phase-locked, the charge-pump current

value is automatically switched to LOW.

Table 1

Differences between TSA5526 and TSA5527

DATA WORD

18-bit

19-bit

TSA5526; TSA5527

This action is taken to improve the carrier-to-noise ratio.

The status of this feature can be read in the ACPS flag

during a read operation on the I

C-bus (see Table 8).

C-bus format (SW = LOW)

Five serial bytes (including address byte) are required to

address the device, select the VCO frequency, program

the four PNP band switch buffers, set the charge-pump

current and the reference divider ratio.

The device has three independent I

C-bus addresses

which can be selected by applying a specific voltage on the

CE input (see Table 5). The general address C2 is always

valid. When the I

C-bus format is fully used, TSA5526 and

TSA5527 are equal.

3-wire bus format (SW = V

CC1

or open-circuit)

Data is transmitted to the device during a HIGH level on

the CE input (enable line pin 15). The device is compatible

with 18-bit and 19-bit data formats. The first four bits are

used to program the PNP band switch buffers and the

remaining bits are used to control the programmable

divider. A 27-bit data format may also be used to set the

charge-pump current, the reference divider ratio and for

test purposes. The differences between TSA5526 and

TSA5527 are given in Table 1.

When the 27-bit format is used, the TSA5526 and

TSA5527 are equal and the reference divider is controlled

by the RSA and RSB bits (see Table 7 and

Figs 3, 4 and 5).

TYPE NUMBER

TSA5526

TSA5527

Notes

REFERENCE DIVIDER

512

(1)

1024

(1)

640

(2)

FREQUENCY STEP (kHz)

62.5

31.25

1. The selection of the reference divider is given by an automatic identification of the data word length.

2. The reference divider is set to 640 at power-on reset.

1996 Sep 24

1996 Sep 24

V tune

f div

DIVIDER

512/640/1024

f ref

RSA RSB

T2,T1,T0

15-BIT FREQUENCY

IN-LOCK

DETECTOR

LOGIC

lock

RSA,RSB

4-BIT BAND SWITCH

GATE

7-BIT CONTROL

VCC1

VEE

AMP

BLOCK DIAGRAM

Philips Semiconductors

handbook, full pagewidth

PRESCALER

DIVIDE-BY-8

CHARGE

PUMP

15-BIT

PROGRAMMABLE

DIVIDER

XTAL

OSCILLATOR

DIGITAL

PHASE

COMPARATOR

1.3 GHz universal bus-controlled

TV synthesizers

POWER-ON

RESET

SCL

T2,T1,T0

VCC2

BS1

BS2

BS3

BS4

SDA

C/3-WIRE BUS

TRANSCEIVER

5-LEVEL

ADC

TSA5526

TSA5527

MBE327

LOCK/

ADC

TSA5526; TSA5527

Product speciﬁcation

Fig.1 Block diagram.

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Description	IC PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16, 4.40 MM, PLASTIC, SSOP-16, PLL or Frequency Synthesis Circuit	IC PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16, 4.40 MM, PLASTIC, SSOP-16, PLL or Frequency Synthesis Circuit	IC PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16, 3.90 MM, PLASTIC, SO-16, PLL or Frequency Synthesis Circuit	IC PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16, 3.90 MM, PLASTIC, SO-16, PLL or Frequency Synthesis Circuit	IC PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16, 4.40 MM, PLASTIC, SSOP-16, PLL or Frequency Synthesis Circuit	IC PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16, 3.90 MM, PLASTIC, SO-16, PLL or Frequency Synthesis Circuit	IC PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16, 4.40 MM, PLASTIC, SSOP-16, PLL or Frequency Synthesis Circuit	IC PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16, 3.90 MM, PLASTIC, SO-16, PLL or Frequency Synthesis Circuit
Maker	NXP	NXP	NXP	NXP	NXP	NXP	NXP	NXP
Parts packaging code	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC
package instruction	LSSOP,	LSSOP,	SOP,	SOP,	LSSOP, SSOP16,.25	SOP,	LSSOP,	SOP,
Contacts	16	16	16	16	16	16	16	16
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Other features	ALSO REQUIRES 4.5V TO 13.5V SUPPLY	ALSO REQUIRES 4.5V TO 13.5V SUPPLY	ALSO REQUIRES 4.5V TO 13.5V SUPPLY	ALSO REQUIRES 4.5V TO 13.5V SUPPLY	ALSO REQUIRES 4.5V TO 13.5V SUPPLY	ALSO REQUIRES 4.5V TO 13.5V SUPPLY	ALSO REQUIRES 4.5V TO 13.5V SUPPLY	ALSO REQUIRES 4.5V TO 13.5V SUPPLY
Analog Integrated Circuits - Other Types	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
length	5.2 mm	5.2 mm	9.9 mm	9.9 mm	5.2 mm	9.9 mm	5.2 mm	9.9 mm
Number of functions	1	1	1	1	1	1	1	1
Number of terminals	16	16	16	16	16	16	16	16
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-20 °C	-20 °C	-20 °C	-20 °C	-20 °C	-20 °C	-20 °C	-20 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LSSOP	LSSOP	SOP	SOP	LSSOP	SOP	LSSOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	SMALL OUTLINE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.5 mm	1.5 mm	1.75 mm	1.75 mm	1.5 mm	1.75 mm	1.5 mm	1.75 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	1.27 mm	1.27 mm	0.65 mm	1.27 mm	0.65 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
width	4.4 mm	4.4 mm	3.9 mm	3.9 mm	4.4 mm	3.9 mm	4.4 mm	3.9 mm
JESD-609 code	e4	e4	e4	e4	e4	e4	-	e4
Terminal surface	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	-	NICKEL PALLADIUM GOLD

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