INTEGRATED CIRCUITS
DATA SHEET
TSA5526; TSA5527
1.3 GHz universal bus-controlled
TV synthesizers
Product specification
Supersedes data of 1995 Mar 22
File under Integrated Circuits, IC02
1996 Sep 24
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
FEATURES
•
Complete 1.3 GHz single chip system
•
Four PNP band switch buffers (40 mA)
•
33 V output tuning voltage
•
In-lock detector
•
5-step ADC
•
15-bit programmable divider
•
Programmable reference divider ratio
(512, 640 or 1024)
•
Programmable charge-pump current (60 or 280
µA)
•
Programmable automatic charge-pump current switch
•
Varicap drive disable
•
Universal bus protocol I
2
C-bus or 3-wire bus:
– bus protocol for 18 or 19 bits transmission
(3-wire bus)
– extra protocol for 27 bits for test and features
(3-wire bus)
– address plus 4 data bytes transmission (I
2
C-bus write
mode)
– address plus 1 status byte transmission (I
2
C-bus
read mode)
– three independent I
2
C-bus addresses
•
Low power and low radiation.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TSA5526M
TSA5526T
TSA5527M
TSA5527T
TSA5526AM
TSA5526AT
TSA5527AM
TSA5527AT
SSOP16
SO16
SSOP16
SO16
SSOP16
SO16
SSOP16
SO16
DESCRIPTION
APPLICATIONS
TSA5526; TSA5527
•
TV tuners and front ends
•
VCR tuners.
VERSION
SOT369-1
SOT109-1
SOT369-1
SOT109-1
SOT369-1
SOT109-1
SOT369-1
SOT109-1
plastic shrink small outline package; 16 leads; body width 4.4 mm
plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads; body width 4.4 mm
plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads; body width 4.4 mm
plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads; body width 4.4 mm
plastic small outline package; 16 leads; body width 3.9 mm
1996 Sep 24
2
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
QUICK REFERENCE DATA
SYMBOL
V
CC1
V
CC2
I
CC1
I
CC2
f
RF
V
i(RF)
PARAMETER
supply voltage (+5 V)
band switch supply voltage (12 V)
supply current
band switch supply current
RF input frequency
RF input voltage
f
i
= 80 to 150 MHz
f
i
= 150 to 1000 MHz
f
i
= 1000 to 1300 MHz
f
xtal
I
o(PNP)
P
tot
T
stg
T
amb
Notes
1. One band switch buffer ON, I
o
= 40 mA.
crystal oscillator input frequency
PNP band switch buffers output
current
total power dissipation
storage temperature
operating ambient temperature
note 2
note 3
note 1
CONDITIONS
MIN.
4.5
V
CC1
−
−
64
−25
−28
−15
3.2
4
−
−40
−20
TSA5526; TSA5527
TYP.
−
12
20
50
−
−
−
−
4.0
−
250
−
−
MAX.
5.5
13.5
25
55
1300
3
3
3
4.48
50
400
+150
+85
V
V
UNIT
mA
mA
MHz
dBm
dBm
dBm
MHz
mA
mW
°C
°C
2. One band switch buffer ON, I
o
= 40 mA; two buffers ON, maximum sum of I
o
= 50 mA.
3. The power dissipation is calculated as follows:
P
D
=
V
CC1
×
I
CC1
+
V
CC2
× (
I
CC2
–
I
o
)
+
I
o
×
V
CE
(
satPNP
)
+
(
V33
⁄
2
) ⁄
27 kΩ.
2
1996 Sep 24
3
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
GENERAL DESCRIPTION
The device is a single-chip PLL frequency synthesizer
designed for TV and VCR tuning systems. The circuit
consists of a divide-by-eight prescaler with its own
preamplifier, a 15-bit programmable divider, a crystal
oscillator and its programmable reference divider and a
phase/frequency detector combined with a charge-pump
which drives the tuning amplifier and the 33 V output.
Four high-current PNP band switch buffers are provided
for band switching. Two PNP buffers can be switched on
simultaneously. The sum of the collector currents is limited
to 50 mA.
Depending on the reference divider ratio (512, 640 or
1024), the phase comparator operates at 3.90625 kHz,
6.25 kHz or 7.8125 kHz using a 4 MHz crystal.
The device can be controlled in accordance with the
I
2
C-bus format or the 3-wire bus format depending on the
voltage applied to the SW input (see Table 2). In the 3-wire
bus mode (SW = HIGH) pin 12 is the LOCK output.
The lock output is LOW when the PLL loop is locked. In the
I
2
C-bus mode (SW = LOW) the LOCK detector bit FL is set
to logic 1 when the loop is locked and is read on the SDA
line (status byte) during a read operation. The ADC input
is available on pin 12 for AFC control in the I
2
C-bus mode
only. The ADC code is read during a read operation on the
I
2
C-bus. In the test mode pin 12 is used as a test output for
f
ref
and
1
⁄
2
f
div
in the I
2
C-bus mode and the 3-wire bus mode
(see Table 6).
When the automatic charge-pump current switch mode is
activated, depending on the device given in Table 6, and
when the loop is phase-locked, the charge-pump current
value is automatically switched to LOW.
Table 1
Differences between TSA5526 and TSA5527
DATA WORD
18-bit
19-bit
19-bit
TSA5526; TSA5527
This action is taken to improve the carrier-to-noise ratio.
The status of this feature can be read in the ACPS flag
during a read operation on the I
2
C-bus (see Table 8).
I
2
C-bus format (SW = LOW)
Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the four PNP band switch buffers, set the charge-pump
current and the reference divider ratio.
The device has three independent I
2
C-bus addresses
which can be selected by applying a specific voltage on the
CE input (see Table 5). The general address C2 is always
valid. When the I
2
C-bus format is fully used, TSA5526 and
TSA5527 are equal.
3-wire bus format (SW = V
CC1
or open-circuit)
Data is transmitted to the device during a HIGH level on
the CE input (enable line pin 15). The device is compatible
with 18-bit and 19-bit data formats. The first four bits are
used to program the PNP band switch buffers and the
remaining bits are used to control the programmable
divider. A 27-bit data format may also be used to set the
charge-pump current, the reference divider ratio and for
test purposes. The differences between TSA5526 and
TSA5527 are given in Table 1.
When the 27-bit format is used, the TSA5526 and
TSA5527 are equal and the reference divider is controlled
by the RSA and RSB bits (see Table 7 and
Figs 3, 4 and 5).
TYPE NUMBER
TSA5526
TSA5526
TSA5527
Notes
REFERENCE DIVIDER
512
(1)
1024
(1)
640
(2)
FREQUENCY STEP (kHz)
62.5
31.25
50
1. The selection of the reference divider is given by an automatic identification of the data word length.
2. The reference divider is set to 640 at power-on reset.
1996 Sep 24
4
1996 Sep 24
9
CP
V tune
10
f div
DIVIDER
512/640/1024
f ref
CP
RSA RSB
T2,T1,T0
15-BIT FREQUENCY
REGISTER
IN-LOCK
DETECTOR
LOGIC
lock
RSA,RSB
3
OS
4-BIT BAND SWITCH
REGISTER
GATE
7-BIT CONTROL
REGISTER
2
VCC1
VEE
AMP
BLOCK DIAGRAM
Philips Semiconductors
handbook, full pagewidth
RF
1
PRESCALER
DIVIDE-BY-8
CHARGE
PUMP
15-BIT
PROGRAMMABLE
DIVIDER
16
XTAL
XTAL
OSCILLATOR
DIGITAL
PHASE
COMPARATOR
1.3 GHz universal bus-controlled
TV synthesizers
POWER-ON
RESET
13
SCL
14
5
T2,T1,T0
4
VCC2
BS1
BS2
BS3
BS4
8
7
6
5
SDA
15
I
2
C/3-WIRE BUS
TRANSCEIVER
CE
SW
11
5-LEVEL
ADC
12
TSA5526
TSA5527
MBE327
LOCK/
ADC
TSA5526; TSA5527
Product specification
Fig.1 Block diagram.
Microcontroller MCU
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