Operated at Commercial and Industrial Temperature Ranges.
PRELIMINARY
CMOS SRAM
Revision History
Rev No.
Rev. 0.0
Rev. 1.0
History
Initial release with Preliminary.
1.1 Removed Low power Version.
1.2 Removed Data Retention Characteristics.
1.3 Changed I
SB1
to 20mA
Relax D.C parameters.
Item
I
CC
12ns
15ns
20ns
Previous
150mA
145mA
140mA
Current
190mA
185mA
180mA
Final
Draft Data
Feb. 12. 1999
Mar. 29. 1999
Remark
Preliminary
Preliminary
Rev. 2.0
Aug. 19. 1999
Preliminary
Rev. 3.0
3.1 Delete Preliminary
3.2 Update D.C parameters and 10ns part.
I
CC
-
190mA
185mA
180mA
Previous
I
sb
70mA
I
sb1
20mA
I
CC
150mA
140mA
130mA
120mA
Current
I
sb
60mA
I
sb1
10mA
Mar. 27. 2000
10ns
12ns
15ns
20ns
Rev. 4.0
Add Low Power-Ver.
Apr. 24. 2000
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 4.0
April 2000
KM64V4002C/CL, KM64V4002CI/CLI
1M x 4 Bit (with OE)High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 10,12,15,20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 60mA(Max.)
(CMOS) : 10mA(Max.)
1.2mA(Max.) L-Ver. only
Operating
KM64V4002C/CL-10 : 150mA(Max.)
KM64V4002C/CL-12 : 140mA(Max.)
KM64V4002C/CL-15 : 130mA(Max.)
KM64V4002C/CL-20 : 120mA(Max.)
• Single 3.3±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention ; L-Ver. only
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM64V4002CJ : 32-SOJ-400
PRELIMINARY
CMOS SRAM
GENERAL DESCRIPTION
The KM64V4002C is a 4,194,304-bit high-speed Static Random
Access Memory organized as 1,048,576 words by 4 bits. The
KM64V4002C uses 4 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM64V4002C is packaged
in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION
(Top View)
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
A
19
A
18
A
17
A
16
A
15
OE
ORDERING INFORMATION
KM64V4002C/CL-10/12/15/20
KM64V4002CI/CLI-10/12/15/20
Commercial Temp.
Industrial Temp.
A
1
A
2
A
3
A
4
CS
I/O
1
26 I/O
4
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
I/O
1
~I/O
4
Vcc
Vss
SOJ
25
24
Vss
Vcc
Pre-Charge Circuit
I/O
2
WE
A
5
23 I/O
3
22
21
20
19
18
A
14
A
13
A
12
A
11
A
10
Row Select
A
6
Memory Array
1024 Rows
1024 x 4 Columns
A
7
A
8
A
9
17 N.C
Data
Cont.
CLK
Gen.
A
10
I/O Circuit
Column Select
PIN FUNCTION
Pin Name
A
0
- A
19
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
No Connection
A
12
A
14
A
16
A
18
A
11
A
13
A
15
A
17
A
19
WE
CS
OE
CS
WE
OE
I/O
1
~ I/O
4
V
CC
V
SS
N.C
-2-
Rev 4.0
April 2000
KM64V4002C/CL, KM64V4002CI/CLI
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
T
A
Rating
-0.5 to 4.6
-0.5 to 4.6
1.0
-65 to 150
0 to 70
-40 to 85
PRELIMINARY
CMOS SRAM
Unit
V
V
W
°C
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3*
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3**
0.8
Unit
V
V
V
V
* The above parameters are also guaranteed at industrial temperature range.
**
V
IL
(Min) = -2.0V a.c(Pulse Width
≤
8ns) for I
≤
20mA.
***
V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA.
DC AND OPERATING CHARACTERISTICS*
(
T
A
=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
Com.
10ns
12ns
15ns
20ns
Ind.
10ns
12ns
15ns
20ns
Standby Current
I
SB
I
SB1
Min. Cycle, CS=V
IH
f=0MHz, CS≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
Normal
L-ver.
Test Conditions
Min
-2
-2
-
-
-
-
-
-
-
-
-
-
-
-
2.4
Max
2
2
150
140
130
120
165
155
145
135
60
10
1.2
0.4
-
V
V
mA
Unit
µA
µA
mA
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
7
Unit
pF
pF
-3-
Rev 4.0
April 2000
KM64V4002C/CL, KM64V4002CI/CLI
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
* The above test conditions are also applied at industrial temperature range.
PRELIMINARY
CMOS SRAM
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+3.3V
R
L
= 50Ω
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
319Ω
D
OUT
353Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
KM64V4002C-10
KM64V4002C-12
KM64V4002C-15
KM64V4002C-20
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
Symbol
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
PU
t
PD
Min
10
-
-
-
3
0
0
0
3
0
-
Max
-
10
10
5
-
-
5
5
-
-
10
Min
12
-
-
-
3
0
0
0
3
0
-
Max
-
12
12
6
-
-
6
6
-
-
12
Min
15
-
-
-
3
0
0
0
3
0
-
Max
-
15
15
7
-
-
7
7
-
-
15
Min
20
-
-
-
3
0
0
0
3
0
-
Max
-
20
20
9
-
-
9
9
-
-
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
-4-
Rev 4.0
April 2000
KM64V4002C/CL, KM64V4002CI/CLI
WRITE CYCLE*
KM64V4002C-10
KM64V4002C-12
KM64V4002C-15
PRELIMINARY
CMOS SRAM
KM64V4002C-20
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
WR
t
WHZ
t
DW
t
DH
t
OW
Min
10
7
0
7
7
10
0
0
5
0
3
Max
-
-
-
-
-
-
-
6
-
-
-
Min
12
8
0
8
8
12
0
0
6
0
3
Max
-
-
-
-
-
-
-
6
-
-
-
Min
15
10
0
10
10
15
0
0
7
0
3
Max
-
-
-
-
-
-
-
7
-
-
-
Min
20
12
0
12
12
20
0
0
9
0
3
Max
-
-
-
-
-
-
-
9
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
RC
Address
t
OH
Data Out
Previous Valid Data
t
AA
Valid Data
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
t
RC
Address
t
AA
t
CO
t
OE
OE
t
OLZ
Data out
V
CC
Current
I
CC
I
SB
t
LZ(4,5)
Valid Data
t
PU
50%
t
PD
50%
t
OH
t
HZ(3,4,5)
CS
t
OHZ
NOTES(READ
CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
±200mV
from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
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Embedded System
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