PLX448M-65 datasheet, PDF - EEWORLD Datasheet

PLX448M-65: DescriptionUV PLD, 65ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, WINDOWED, CERDIP-24; CategoryProgrammable logic devices Programmable logic; File Size711KB，12 Pages; ManufacturerBroadcom

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PLX448M-65 Overview

UV PLD, 65ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, WINDOWED, CERDIP-24

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Broadcom
package instruction	0.300 INCH, WINDOWED, CERDIP-24
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Other features	PAL WITH MACROCELLS; 8 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK
Architecture	PAL-TYPE
maximum clock frequency	11.1 MHz
JESD-30 code	R-GDIP-T24
JESD-609 code	e0
length	32.2 mm
Dedicated input times	9
Number of I/O lines	8
Number of entries	26
Output times	8
Number of product terms	88
Number of terminals	24
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	9 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	WDIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE, WINDOW
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	UV PLD
propagation delay	65 ns
Certification status	Not Qualified
Maximum seat height	5.3 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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