TS88915T
LOW SKEW CMOS PLL CLOCK DRIVER
3-State 70 and 100 MHz Versions
DESCRIPTION
The TS88915T Clock Driver utilizes a phazed–locked loop
(PLL) technology to lock its low skew outputs’ frequency and
phase onto an input reference clock. It is designed to provide
clock distribution for high performance microprocessors such
as TS68040, TSPC603E,TSPC603P,TSPC603R, PCI bridge,
RAM’s, MMU’s...
MAIN FEATURES
H
Vcc = 5V
5 %
H
MILITARY TEMPERATURE RANGE
H
TS68040 FULL COMPATIBLE
H
FIVE LOW SKEW OUTPUTS
Five Outputs (Q0-Q4) with Output–to–Output skew < 500
ps each being phase end frequency locked to the SYNC
input.
H
ADDITIONAL OUTPUTS
Three additional outputs are available :
– The 2X_Q output runs twice the system ”Q” frequency.
– The Q/2 output runs at 1/2 the system ”Q” frequency.
– The Q5 output is inverted (180° phase shift).
H
TWO SELECTABLE CLOCK INPUTS
– Two selectable CLOCK inputs are available for test or
redundancy purposes.
– Test Mode pin (PLL_EN) provided for low frequency test-
ing.
– All outputs can go into high impedance (3-state) for board
test purpose.
H
INPUT FREQUENCY RANGE FROM 5MHz to 2X_Q
FMAX
H
THREE INPUT/OUTPUT RATIOS
Input/Output phase–locked frequency ratios of 1:2, 1:1 and
2:1 are available.
H
LOW PART-TO-PART SKEW
The phase variation from part–to–part between the SYNC
and FEEDBACK inputs is less than 550 ps (derived from the
t
PD
specification, which defines the part-to-part skew).
H
CMOS AND TTL COMPATIBLE
– All outputs can drive either CMOS or TTL inputs.
– All inputs are TTL-level compatible.
H
LOCK Indicator (LOCK) indicated a phase–locked
state.
R Suffix
PGA 29
Ceramic Pin grid array
W suffix
LDCC 28
Leaded Ceramic Chip Carrier
SCREENING / QUALITY
This product is manufactured :
H
based upon the generic flow of MIL–STD–883.
H
or according to TCS standard.
April 1999
1/20
TS88915T
SUMMARY
A. GENERAL DESCRIPTION . . . . . . . . . . . . . . 3
1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1. 29-Lead Pin Grid Array (PGA) . . . . . . . . . . . . 4
2.2. 28-Lead Ceramic Leaded Chip Carrier
(LDCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 5
4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . 7
4.1. General requirements . . . . . . . . . . . . . . . . . . . 7
4.2. Static characteristics . . . . . . . . . . . . . . . . . . . . 7
4.2.1. DC electrical characteristics . . . . . . . . 7
4.2.2. Capacitance and power specifications 8
4.3. Dynamic characteristics . . . . . . . . . . . . . . . . .
4.3.1. Frequency applications . . . . . . . . . . .
4.3.2. SYNC input timing requirements . . .
4.3.3. AC characteristics . . . . . . . . . . . . . . . .
8
8
8
8
B. DETAILED SPECIFICATIONS . . . . . . . . . . . 6
1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . . 6
3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2. Design and construction . . . . . . . . . . . . . . . . .
3.2.1. Terminal connections . . . . . . . . . . . . .
3.2.2. Lead material and finish . . . . . . . . . . .
3.2.3. Package . . . . . . . . . . . . . . . . . . . . . . . .
6
6
6
6
5. APPLICATION INFORMATION . . . . . . . . . . . . . . 11
5.1. General AC specification notes . . . . . . . . . . 11
5.2. Timing notes . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Notes concerning loop filter and board layout
issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4. TS88915T system level testing functionality 17
6. PREPARATION FOR DELIVERY . . . . . . . . . . . . . 17
6.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2. Certificate of compliance . . . . . . . . . . . . . . . . 17
7. HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8. PACKAGE MECHANICAL DATA . . . . . . . . . . . . 18
9. ORDERING INFORMATION . . . . . . . . . . . . . . . . . 19
3.3. Electrical characteristics . . . . . . . . . . . . . . . . . 6
3.4. Mechanical and environment . . . . . . . . . . . . . 7
3.5. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
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TS88915T
A. GENERAL DESCRIPTION
1. INTRODUCTION
The TS88915T is a CMOS PLL Clock Driver using phase–locked loop (PLL) technology. The PLL allows the high current, low skew
outputs to lock onto a single input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows
the TS88915T to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Multiple 88915’s can
lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to
multiple boards (see Figure 12).
Figure 1 shows TS88915T block diagram.
FEEDBACK
LOCK
SYNC[0]
0
M
U
X
PHASE/FREQ.
DETECTOR
CHARGE PUMP/
LOOP FILTER
VOLTAGE
CONTROLLED
OSCILLATOR
SYNC[1]
1
EXT. REC NETWORK
(RC1 pin)
REF_SEL
0
PLL_EN
MUX
1
2X_Q
D
(+1)
1
DIVIDE
BY TWO
(+2)
0
D
CP
FREQ_SEL
OE/RST
D
CP
R
R
M
U
X
CP
R
Q
Q
Q0
Q
Q
Q1
Q
Q
Q2
D
CP
R
Q
Q
Q3
D
CP
R
Q
Q
Q4
D
CP
R
Q
Q
Q5
D
CP
R
Q
Q
Q/2
Figure 1 :
TS88915T Block Diagram
(All versions)
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TS88915T
2. PIN ASSIGNMENTS
2.1. 29-Lead Pin Grid Array (PGA)
F
F/SL
E
GNDA
D
VCCA
C
SYC0
B
FDBK
A
NC
VCC
GND
Q4
Q*2
RST
Q5
VCC
Q/2
GND
R/SL
Q3
VCC
RC1
TS88915T
(BOTTOM VIEW)
GND
Q2
SYC1
GND
Q1
P/EN
LOCK
Q0
VCC
GND
1
2
3
4
5
6
Figure 2 :
29-Lead PGA (Bottom View)
2.2. 28-Lead Ceramic Leaded Chip Carrier (LDCC)
OE/RST
4
FEEDBACK
5
VCC
3
Q5
2
GND
1
Q4
28
VCC
27
2X_Q
26
25
Q/2
REF_SEL
6
24
GND
SYNC[0]
7
23
Q3
VCC (AN)
8
TS88915T
(TOP VIEW)
22
VCC
RC1
9
21
20
Q2
GND (AN)
10
GND
SYNC[1]
11
12
13
14
Q0
15
VCC
16
Q1
17
18
19
LOCK
FREQ_SEL GND
GND PLL_EN
Figure 3 :
28–Lead LDCC (Top View)
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TS88915T
3. SIGNAL DESCRIPTION
Pin Name
SYNC[0]
SYNC[1]
REF_SEL
FREQ_SEL
FEEDBACK
RC1
Q(0–4)
Q5
2x_Q
Q/2
LOCK
OE/RST
PLL_EN
VCC, GND
Num
1
1
1
1
1
1
5
1
1
1
1
1
1
11
I/O
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Input
Input
Power
Reference clock input
Reference clock input
Chooses reference between SYNC[0] and SYNC[1]
Doubles VCO internal frequency
Feedback input to phase detector
Input for external RC network
Clock output (locked to SYNC)
Inverse of clock output
2 x clock output (Q) frequency (synchronous)
Clock output (Q) frequency
B
2 (synchronous)
Indicates phase lock has been achieved (high when locked)
Output Enable / Asynchronous reset (active low)
Disables phase–lock for low frequency testing
Power and Ground pins
Pins 8 and 10 are ”analog” supply pins for internal PLL only
Signal function
Table 1 :
Signal index
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