– Sector erase (SE) command (D8h) for 64 KB and 256 KB sectors
– Sub-sector erase (P4E) command (20h) for 4 KB sectors
(for uniform 64-KB sector device only)
– Sub-sector erase (P8E) command (40h) for 8 KB sectors
(for uniform 64-KB sector device only)
Power saving standby mode
– Standby Mode 80 µA (typical)
– Deep Power-Down Mode 3 µA (typical)
Cycling endurance
– 100,000 cycles per sector typical
Data retention
– 20 years typical
Memory Protection Features
Memory protection
– W#/ACC pin works in conjunction with Status Register Bits to
protect specified memory areas
– Status Register Block Protection bits (BP2, BP1, BP0) in status
Device ID
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward
compatibility
Publication Number
S25FL129P_00
Revision
08
Issue Date
September 21, 2012
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient pro-
duction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid com-
binations offered may occur.
D a t a
S h e e t
General Description
The S25FL129P is a 3.0 Volt (2.7V to 3.6V), single-power-supply Flash memory device. The device is offered
in two configurations: 256 uniform 64 KB sectors with the two (Top or Bottom) 64 KB sectors further split up
into thirty-two 4 KB sub sectors, or 64 uniform 256 KB sectors. The S25FL129P device is backward
compatible with the S25FL128P (uniform 256 KB sector) device.
The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are
designed to be programmed in-system with the standard system 3.0-volt V
CC
supply.
The S25FL129P device adds the following high-performance features using 5 new instructions:
Dual Output Read using both SI and SO pins as output pins at a clock rate of up to 80 MHz
Quad Output Read using SI, SO, W#/ACC and HOLD# pins as output pins at a clock rate of up to 80 MHz
Dual I/O High Performance Read using both SI and SO pins as input and output pins at a clock rate of up
to 80 MHz
Quad I/O High Performance Read using SI, SO, W#/ACC and HOLD# pins as input and output pins at a
clock rate of up to 80 MHz
Quad Page Programming using SI, SO, W#/ACC and HOLD# pins as input pins to program data at a clock
rate of up to 80 MHz
The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device
supports Sector Erase and Bulk Erase commands.
Each device requires only a 3.0-volt power supply (2.7V to 3.6V) for both read and write functions. Internally
generated and regulated voltages are provided for the program operations. This device requires a high
voltage supply to the W#/ACC pin to enable the Accelerated Programming mode.
The S25FL129P device also offers a One-Time Programmable area (OTP) of up to 128-bits (16 bytes) for
permanent secure identification and an additional 490 bytes of OTP space for other use. This OTP area can
be programmed or read using the OTPP or OTPR instructions.
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