PHKD6N02LT
Dual N-channel TrenchMOS logic level FET
Rev. 04 — 27 April 2010
Product data sheet
1. Product profile
1.1 General description
Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Suitable for logic level gate drive
sources
1.3 Applications
Battery chargers
DC-to-DC convertors
Notebook computers
Portable equipment
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
Quick reference data
Parameter
drain-source voltage
drain current
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
sp
= 25 °C; Single device
conducting; see
Figure 1;
see
Figure 3
T
sp
= 25 °C; see
Figure 2
Min
-
-
Typ
-
-
Max Unit
20
V
10.9 A
P
tot
total power
dissipation
-
-
4.17 W
Static characteristics
R
DSon
drain-source on-state V
GS
= 2.5 V; I
D
= 3 A; T
j
= 25 °C
resistance
gate-drain charge
V
GS
= 5 V; I
D
= 6 A; V
DS
= 16 V;
T
j
= 25 °C; see
Figure 11
-
25
35
mΩ
Dynamic characteristics
Q
GD
-
6
-
nC
Nexperia
PHKD6N02LT
Dual N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
Pinning information
Symbol Description
S1
G1
S2
G2
D2
D2
D1
D1
source1
gate1
source2
gate2
drain2
drain2
drain1
drain1
1
4
S1
G1
S2
G2
mbk725
Simplified outline
8
5
Graphic symbol
D1 D1
D2 D2
SOT96-1 (SO8)
3. Ordering information
Table 3.
Ordering information
Package
Name
PHKD6N02LT
SO8
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
Type number
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
sp
= 100 °C; Single device conducting;
see
Figure 1
T
sp
= 25 °C; Single device conducting;
see
Figure 1;
see
Figure 3
I
DM
P
tot
T
stg
T
j
I
S
I
SM
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
sp
= 25 °C
T
sp
= 25 °C; t
p
≤
10 µs; pulsed
T
sp
= 25 °C; t
p
≤
100 µs; pulsed; Single
device conducting; see
Figure 3
T
sp
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
j
≤
150 °C; T
j
≥
25 °C; R
GS
= 20 kΩ
Min
-
-
-12
-
-
-
-
-55
-55
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
Max
20
20
12
6.8
10.9
44
4.17
150
150
3.5
44
Unit
V
V
V
A
A
A
W
°C
°C
A
A
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
PHKD6N02LT
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 04 — 27 April 2010
2 of 13
Nexperia
PHKD6N02LT
Dual N-channel TrenchMOS logic level FET
120
I
der
(%)
80
03aa25
120
P
der
(%)
80
03aa17
40
40
0
0
50
100
150
T
sp
(°C)
200
0
0
50
100
150
T
sp
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of solder point temperature
Fig 2.
Normalized total power dissipation as a
function of solder point temperature
10
2
003aaa300
Limit R
DSon
= V
DS
/I
D
I
D
(A)
10
t
p
= 10
µs
100
µs
1 ms
10 ms
100 ms
DC
1
10
−1
10
−2
10
−1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHKD6N02LT
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 04 — 27 April 2010
3 of 13
Nexperia
PHKD6N02LT
Dual N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-sp)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from
junction to solder point
thermal resistance from
junction to ambient
Conditions
see
Figure 4
minimum footprint; mounted on
printed-circuit board
Min
-
-
Typ
-
70
Max
30
-
Unit
K/W
K/W
10
2
Z
th(j-sp)
(K/W)
δ
= 0.5
10
0.2
0.1
0.05
0.02
1
P
003aaa301
single pulse
δ
=
t
p
T
t
p
t
T
10
−1
10
−4
10
−3
10
−2
10
−1
1
t
p
(s)
10
Fig 4.
Transient thermal impedance from junction to ambient as a function of pulse duration
PHKD6N02LT
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 04 — 27 April 2010
4 of 13
Nexperia
PHKD6N02LT
Dual N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
I
DSS
I
GSS
R
DSon
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
drain leakage current
gate leakage current
drain-source on-state
resistance
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
DS
= 10 V; T
j
= 25 °C;
see
Figure 8
V
DS
= 20 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 20 V; V
GS
= 0 V; T
j
= 150 °C
V
GS
= 12 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -12 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 2.5 V; I
D
= 3 A; T
j
= 25 °C
V
GS
= 5 V; I
D
= 3 A; T
j
= 150 °C;
see
Figure 9;
see
Figure 10
V
GS
= 5 V; I
D
= 3 A; T
j
= 25 °C; see
Figure 9;
see
Figure 10
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
reverse recovery time
recovered charge
I
S
= 6 A; V
GS
= 0 V; T
j
= 25 °C; see
Figure 13
I
S
= 6 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
V
DS
= 20 V; T
j
= 25 °C
V
DS
= 10 V; R
L
= 3.3
Ω;
V
GS
= 5 V;
R
G(ext)
= 4.7
Ω;
T
j
= 25 °C
V
DS
= 10 V; V
GS
= 0 V; f = 1 MHz; T
j
= 25 °C;
see
Figure 12
I
D
= 6 A; V
DS
= 16 V; V
GS
= 5 V; T
j
= 25 °C;
see
Figure 11
-
-
-
-
-
-
-
-
-
-
-
-
-
15.3
2.2
6
950
355
256
15
49
50
23
-
40
7
-
-
-
-
-
-
-
-
-
-
1.2
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
Min
20
0.5
-
-
-
-
-
-
-
Typ
-
-
0.05
-
-
-
25
-
16
Max
-
1.5
10
500
100
100
35
35
20
Unit
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Static characteristics
Source-drain diode
PHKD6N02LT
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 04 — 27 April 2010
5 of 13
京公网安备 11010802033920号
EEWORLD
