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ICS9248F-163-T

Description
Clock Generator, CMOS, PDSO48, SSOP-48
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size294KB,14 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

ICS9248F-163-T Overview

Clock Generator, CMOS, PDSO48, SSOP-48

ICS9248F-163-T Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
package instructionSSOP, SSOP48,.4
Reach Compliance Codeunknown
JESD-30 codeR-PDSO-G48
JESD-609 codee0
Number of terminals48
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Encapsulate equivalent codeSSOP48,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
power supply2.5,3.3 V
Certification statusNot Qualified
Maximum slew rate180 mA
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Integrated
Circuit
Systems, Inc.
ICS9248-163
Preliminary Product Preview
AMD - K7™ System Clock Chip
Recommended Application:
VIA KX133 style chipset
Output Features:
1 - Differential pair open drain CPU clocks
1 - CPU clock @ 3.3V
13 - SDRAM @ 3.3V
6 - PCI @3.3V,
1 - 48MHz, @3.3V fixed.
1 - 24/48MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
Features:
Up to 166MHz frequency support
Support power management: CPU stop and Power down
Mode from I
2
C programming.
Spread spectrum for EMI control
(± 0.25% center spread).
Uses external 14.318MHz crystal
Pin Configuration
VDDREF
REF0/CPU_STOP*
GND
X1
X2
VDD
*MODE/PCICLK_F
*FS3/PCICLK0
GND
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1/FS2*
GND
CPUCLK
GND
CPUCLKC0
CPUCLKT0
VDDA
PD#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24/48MHz/FS1*
* Internal Pull-up Resistor of 120K to VDD
48-Pin 300mil SSOP
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
REF (1:0)
CPUCLK
CPU
DIVDER
Stop
Functionality
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
90.00
95.00
101.00
102.00
100.90
103.00
105.00
100.00
107.00
109.00
110.00
111.00
113.00
115.00
117.00
133.30
PCICLK
(MHz)
30.00
31.67
33.67
34.00
33.57
34.33
35.00
33.33
35.67
36.33
36.67
37.00
37.67
38.33
39.00
33.33
CPUCLKC0
CPUCLKT0
SEL24_48#
SDATA
SCLK
FS (3:0)
PD#
CPU_STOP#
BUFFER IN
Control
Logic
Config.
Reg.
PCI
DIVDER
PCICLK (4:0)
PCICLK_F
SDRAM
DRIVER
SDRAM (11:0)
SDRAM_OUT
9248-163 Rev A 9/22/00
Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
ICS9248-163
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