5962R1220201VXC datasheet, PDF

Datasheet> All Categories > Power/power management> The power supply circuit> 5962R1220201VXC

5962R1220201VXC: Description1.2A SWITCHING REGULATOR, 1200kHz SWITCHING FREQ-MAX, CQFP64, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, QFP-64; CategoryPower/power management The power supply circuit; File Size508KB，23 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

Download Datasheet Parametric Compare View All

5962R1220201VXC Overview

1.2A SWITCHING REGULATOR, 1200kHz SWITCHING FREQ-MAX, CQFP64, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, QFP-64

5962R1220201VXC Parametric

Parameter Name	Attribute value
Objectid	1209291444
Parts packaging code	QFP
package instruction	QFF, QFL64,.55SQ,25
Contacts	64
Reach Compliance Code	compliant
ECCN code	USML XV(E)
Samacsys Manufacturer	Intersil
Samacsys Modified On	2020-04-06 16:22:53
Other features	ADJUSTABLE MODE FROM 0.8 TO 4.675
Analog Integrated Circuits - Other Types	SWITCHING REGULATOR
control mode	CURRENT-MODE
Control Technology	PULSE WIDTH MODULATION
Maximum input voltage	5.5 V
Minimum input voltage	3 V
Nominal input voltage	3.3 V
JESD-30 code	S-CQFP-F64
JESD-609 code	e4
length	14.15 mm
Number of functions	1
Number of terminals	64
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Maximum output current	1.2 A
Nominal output voltage	1.8 V
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF
Encapsulate equivalent code	QFL64,.55SQ,25
Package shape	SQUARE
Package form	FLATPACK
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class V
Maximum seat height	2.67 mm
surface mount	YES
Switch configuration	BUCK
Maximum switching frequency	1200 kHz
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	FLAT
Terminal pitch	0.635 mm
Terminal location	QUAD
total dose	100k Rad(Si) V
width	14.15 mm

Preview

Download Datasheet

View All

Rad Hard and SEE Hard 12A Synchronous Buck

Regulator with Multi-Phase Current Sharing

ISL70002SEH

The ISL70002SEH is a radiation hardened and SEE hardened

high efficiency monolithic synchronous buck regulator with

integrated MOSFETs. This single chip power solution operates

over an input voltage range of 3V to 5.5V and provides a tightly

regulated output voltage that is externally adjustable from 0.8V

to ~85% of the input voltage. Output load current capacity is

12A for T

≤

+150°C. Two ISL70002SEH devices configured to

current share can provide 19A total output current, assuming

±27% worst-case current share accuracy.

The ISL70002SEH utilizes peak current-mode control with

integrated error amp compensation and pin selectable slope

compensation. Switching frequency is also pin selectable to

either 1MHz or 500kHz. Two ISL70002SEH devices can be

synchronized 180° out-of-phase to reduce input RMS ripple

current.

High integration makes the ISL70002SEH an ideal choice to

power small form factor applications. Two devices can be

synchronized to provide a complete power solution for large

scale digital ICs, like field programmable gate arrays (FPGAs),

that require separate core and I/O voltages.

Features

• DLA

SMD#5962-12202

• 12A Output Current for a Single Device (at T

= +150

• 19A Output Current for Two Paralleled Devices

• 1MHz or 500kHz Switching Frequency

• 3V to 5.5V Supply Voltage Range

• ±1% Ref. Voltage (Line, Load, Temp. & Rad.)

• Pre-Biased Load Compatible

• Redundancy/Junction Isolation: Exceptional SET Performance

• Excellent Transient Response

• High Efficiency > 90%

• Two ISL70002SEH Synchronization, Inverted-Phase

• Comparator Input for Enable and Power-Good

• Adjustable Analog Soft-Start

• Input Undervoltage, Output Undervoltage and Adjustable

Output Overcurrent Protection

• QML Qualified per MIL-PRF-38535

• Full Mil-Temp Range Operation (-55

C to +125

• Radiation Environment

- High Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 krad(Si)

- ELDRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 krad(Si)*

*Level guaranteed by characterization; “EH” version is

production tested to 50 krad(Si).

• SEE Hardness

- SEFI LET

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43MeV/mg/cm

- SET LET

. . . . . . . . . . . . . . . . . . . . . . . . . . 86.4MeV/mg/cm

- SEL and SEB LET

. . . . . . . . . . . . . . . . . . 86.4MeV/mg/cm

Applications

• FPGA, CPLD, DSP, CPU Core and I/O Voltages

• Low-Voltage, High-Density Distributed Power Systems

CH1 MASTER LX + 20V

CH2 SLAVE LX + 15V

CH3 VOUT x 10

EFFICIENCY (%)

-6

LOAD CURRENT (A)

-4

-2

AMPLITUDE (V)

CH4 SYNC

TIME (µs)

FIGURE 1. EFFICIENCY 5V INPUT TO 2.5V OUTPUT, T

= +25°C

FIGURE 2. 2-PHASE SET PERFORMANCE at 86.4MeV/mg/cm

April 5, 2012

FN8264.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ISL70002SEH

Pin Descriptions

(Continued)

PIN NUMBER

3, 5, 7

PIN NAME

ISHREFA/B/C

DESCRIPTION

If configured as a current share Master (ISHSL = DGND, ISHEN = DVDD), the ISHREFA/B/C pins provide a

reference output current equal to 100uA each. If configured as a current share Slave (ISHSL = DVDD,

ISHEN = DVDD), the ISHREFA/B/C pins accept a reference input current. For a current share Slave, this input

current is used together with the ISHA/B/C current to determine the Master’s redundant A/B/C error amp

output current. If using current share, tie ISHREFA/B/C of the MASTER to ISHREFA/B/C of the Slave. If not using

current share, tie ISHREFA/B/C to DVDD. The purpose of the reference current is to reduce the impact of

external noise coupling onto ISHA/B/C. ISHREFA/B/C are tri-stated prior to a valid POR

and when ISHEN = DGND.

This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1Ω

resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. AVDD should

be the same voltage as DVDD and PVINx (±200mV).

This pin is the analog ground associated with the internal analog control circuitry. Connect this pin directly to

the PCB ground plane.

This pin is the digital ground associated with the internal digital control circuitry. Connect this pin directly to the

PCB ground plane.

This pin is the bias supply input to the internal digital control circuitry. Locally filter this pin to DGND using a 1Ω

resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. DVDD should

be the same voltage as AVDD and PVINx (±200mV).

This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output

ramp time in accordance with Equation 2:

⋅

REF

⁄

(EQ. 2)

AVDD

AGND

DGND

DVDD

Where:

= Soft-start output ramp time

= Soft-start capacitor

REF

= Reference voltage (0.6V typical)

= Soft-start charging current (23µA typical)

Soft-start time is adjustable from approximately 2ms to 200ms.

The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.

If using current share, C

of the Slave should be at least twice the C

of the Master.

PGOOD

This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND when the output

voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V,

independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin

to DGND with a 10nF ceramic capacitor to mitigate SEE. If using current share, tie PGOOD of the Master to

PGOOD of the Slave.

ISHCOM is a bidirectional communication line between a current share Master and a current share Slave. If

using current share, tie ISHCOM of the Master to ISHCOM of the Slave. The Master enables the Slave by

resistively (~ 8.5kΩ) pulling ISHCOM high. The Slave indicates an over-current fault condition to the Master by

pulling ISHCOM low. To mitigate SET, connect a 47pF ceramic capacitor from ISHCOM to the PCB ground plane.

If not using current share this pin should be floated or connected to the PCB ground plane. ISHCOM is tri-stated

if ISHEN is low.

This pin is a logic input that is used to configure the IC as a current share Master or Slave. Tie this pin to DVDD

to configure the IC as a current share Slave. Tie this pin to the PCB ground plane to configure the IC as a current

share Master, or if the current share feature is not being used.

This pin is an input that enables/disables the current share feature. To enable the current share feature, tie this

pin to DVDD. To disable the current share feature, tie this pin to the PCB ground plane.

This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V

supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply

voltages between 5V and 3.3V, connect this pin to DGND.

This pin is the test data output of the internal BIT circuitry. Connect this pin to the PCB ground plane.

This pin is the test data input of the internal BIT circuitry. Connect this pin to the PCB ground plane.

This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to the PCB ground plane.

This pin is connected to an internal metal die trace that serves as a sensitive node noise shield. Connect this

pin to the PCB ground plane.

ISHCOM

ISHSL

ISHEN

PORSEL

TDO

TDI

TPGM

GND

FN8264.1

April 5, 2012

ISL70002SEH

Pin Descriptions

(Continued)

PIN NUMBER

PIN NAME

SYNC

DESCRIPTION

When SYNC is configured as an output (clock Master Mode, M/S = DVDD), this pin drives the SYNC input of

another ISL70002SEH with a square ware that is inverted (~180° out-of-phase) from the Master clockdriving

the Master PWM circuits. When configured as an input (clock Slave Mode, M/S = DGND), this pin uses the SYNC

output from another ISL70002SEH or an external clock to drive the clock Slave PWM circuitry. If synchronizing

to an external clock, the clock must be SEE hardened and the frequency must be within the range of 400kHz

to 1.2MHz.

These pins are the power supply inputs to the corresponding internal power blocks. These pins must be

connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly

to PGNDx with ceramic capacitors located as close as possible to the IC. PVINx should be the same voltage as

DVDD and AVDD (±200mV).

These pins are the outputs of the corresponding internal power blocks and should be connected to the output

filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches.

These pins are the power grounds associated with the corresponding internal power blocks. These pins also

provide the ground path for the metal package lid. Connect these pins directly to the PCB ground plane. These

pins should also connect to the negative terminals of the input and output capacitors. Locate the input and

output capacitors as close as possible to the IC.

This pin is the clock Master/Slave input for selecting the direction of the bi-directional SYNC pin. For

SYNC = Output (Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to the

PCB ground plane.

This pin is the oscillator frequency select input. Tie this pin to DVDD to select a 1MHz nominal oscillator

frequency. Tie this pin to the PCB ground plane to select a 500kHz nominal oscillator frequency.

These are No Connect pins that are not connected to anything internally. They should be connected to the PCB

ground plane.

These pins are inputs that comprise a 2-bit code to select the slope compensation (SC) current ramp referred

to the output as shown below.

SC1 = DVDD, SC0 = DVDD: SC = 6.6A/µs for FSEL = DGND

SC1 = DVDD, SC0 = DGND: SC = 3.3A/µs for FSEL = DGND

SC1 = DGND, SC0 = DVDD: SC = 1.6A/µs for FSEL = DGND

SC1 = DGND, SC0 = DGND: SC = 0.8A/µs for FSEL = DGND

SC1 = DVDD, SC0 = DVDD: SC= 13.4A/µs for FSEL = DVDD

SC1 = DVDD, SC0 = DGND: SC = 6.7A/µs for FSEL = DVDD

SC1 = DGND, SC0 = DVDD: SC = 3.4A/µs for FSEL = DVDD

SC1 = DGND, SC0 = DGND: SC = 1.7A/µs for FSEL = DVDD

If using current share, SC0 and SC1 of the Slave MUST match the Master SC0 and SC1.

This pin is the enable input to the IC. This is a comparator type input with a rising threshold of 0.6V and

programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to the PCB ground plane

with a 10nF ceramic capacitor to mitigate SEE.

This pin is a switch to AGND that is active during the soft-start period. It is used to set the redundant A/B peak

overcurrent limit threshold during soft-start. Connect a resistor from OCSSx to OCx in accordance with the

following equation: ROCSSx 600mV / [(IOCSSx - IOCx) /100,000]

where IOCx is the desired peak overcurrent limit during normal operation and IOCSSx is the desired peak

current limit threshold during soft-start.

This pin is a source follower output that is used to set the redundant A/B peak overcurrent limit threshold during

normal operation. Connect a resistor from this pin to the PCB ground plane in accordance with the following

equation: ROCx = 600mV / (IOCx /100,000), where IOCx is the desired peak current limit threshold during

normal operation.

This pin is the internal reference voltage output. Bypass this pin to the PCB ground plane with a 220nF ceramic

capacitor located as close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current

(sourcing or sinking) is available from this pin.

If using current share, tie REF of the Master to REF of the Slave through a 10Ω resistor.

23, 28, 32, 37, 38,

43, 44, 49, 53, 58

PVINx

24, 27, 33, 36, 39,

42, 45, 48, 54, 57

25, 26, 34, 35, 40,

41, 46, 47, 55, 56

LXx

PGNDx

M/S

31, 50

51, 52

FSEL

SC0/1

60, 62

OCSSB/A

61, 63

OCB/A

REF

FN8264.1

April 5, 2012

5962R1220201VXC Related Products

	5962R1220201VXC	5962R1220201V9A	ISL70002SEH	ISL70002SEHF/PROTO
Description	1.2A SWITCHING REGULATOR, 1200kHz SWITCHING FREQ-MAX, CQFP64, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, QFP-64	1.2A SWITCHING REGULATOR, 1200kHz SWITCHING FREQ-MAX, UUC62, ROHS COMPLIANT, DIE-62	1.2 A SWITCHING REGULATOR, 1200 kHz SWITCHING FREQ-MAX, CQFP64	1.2 A SWITCHING REGULATOR, 1200 kHz SWITCHING FREQ-MAX, CQFP64
control mode	CURRENT-MODE	CURRENT-MODE	PEAK CURRENT	PEAK CURRENT
Control Technology	PULSE WIDTH MODULATION	PULSE WIDTH MODULATION	PULSE WIDTH MODULATION	PULSE WIDTH MODULATION
Number of functions	1	1	1	1
Number of terminals	64	62	64	64
Maximum operating temperature	125 °C	125 °C	125 Cel	125 Cel
Minimum operating temperature	-55 °C	-55 °C	-55 Cel	-55 Cel
Maximum output current	1.2 A	1.2 A	1.2 A	1.2 A
surface mount	YES	YES	Yes	Yes
Switch configuration	BUCK	BUCK	BUCK	BUCK
Maximum switching frequency	1200 kHz	1200 kHz	1200 kHz	1200 kHz
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	FLAT	NO LEAD	FLAT	FLAT
Terminal location	QUAD	UPPER	QUAD	QUAD

Recommended Resources

Contact relay output control interface circuit

Photoelectric control automatic shutdown circuit diagram

Simple star zero sequence voltage phase failure protection circuit diagram

Agricultural equipment anti-theft alarm transmitting circuit

Fully automatic contactless AC voltage regulator circuit

Computer motherboard circuit diagram 815 3_37

51 single chip microcomputer tracking car program: [i=s] This post was last edited by ywj1992 on 2014-9-25 14:42 [/i] Share it...; ywj1992 51mcu

SqlCeException Error: Hello everyone, I use .net to connect to the sqlce database. When the program runs to the database publication and subscription, an error occurs. An unhandled exception of type "System.Data.SqlServerC...; XX糖WL Embedded System

RT-Thread porting on Fujitsu Cortex M3 Easy Kit development board (Part 2): RT-Thread transplantation on Fujitsu Cortex M3 Easy Kit development board (I) See https://bbs.eeworld.com.cn/thread-330952-1-1.html After completing "RT-Thread transplantation on Fujitsu Cortex M3 Eas...; yang.aiquan DIY/Open Source Hardware

Please help: Measure voltage frequency, but this program can only measure above 31Hz, below 30Hz, the digital tube display is garbled. Please help, modify it to measure below 30, and display output without garbled...; cai5351301 Microchip MCU

The difference between CC2530dk and CC2530zdk-zll: The difference between CC2530dk and CC2530 zdk-zll is their application...; 是夜126 RF/Wirelessly

FPGA uses library functions to write serial port programs, but the data sent and received are inconsistent.: #include "system.h" #include "altera_avalon_pio_regs.h" #include "altera_avalon_uart_regs.h" #include "sys/alt_irq.h" #include "stdlib.h" //NULL needs to be defined unsigned char rxdata; void Set_baun...; tianma123 FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components