Integrated
Circuit
Systems, Inc.
Preliminary Information
M2050/51/52
SAW PLL
FOR
10G
B
E 64
B
/66
B
FEC
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
FIN_SEL1
GND
P_SEL2
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
FIN_SEL0
FEC_SEL0
FEC_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
G
ENERAL
D
ESCRIPTION
The M2050/51/52 is a VCSO (Voltage Controlled SAW
Oscillator) based clock PLL
designed for FEC clock ratio
translation in 10Gb optical systems
such as 10GbE 64b/66b. It supports
both mapping and de-mapping of
64b/66b encoding and FEC
(Forward Error Correction) clock
multiplication ratios. The ratios are pin-selected from
pre-programming look-up tables.
F
EATURES
◆
Integrated SAW delay line; Output of 15 to 700 MHz
*
◆
Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50Hz to 80MHz)
◆
Pin-selectable PLL divider ratios support 64b/66b and
FEC encoding/decoding ratios:
• M2050: Map 10GbE to LAN, 255/238 FEC, or 255/237 FEC
• M2051: De-map 10GbE LAN or 255/238 FEC to 10GbE
• M2052: De-map 255/237 FEC & 255/238 FEC to 10GbE LAN
28
29
30
31
32
33
34
35
36
M2050
M2051
M2052
(Top View)
18
17
16
15
14
13
12
11
10
P_SEL0
P_SEL1
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
◆
Scalable dividers provide further adjustment of loop
bandwidth as well as jitter tolerance
◆
LVPECL clock output (CML and LVDS options available)
◆
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆
Loss of Lock (LOL) output pin
◆
Narrow Bandwidth control input (NBW Pin)
◆
Hitless Switching (HS) options with or without Phase
Build-out (PBO) available; performance conforms with
SONET (GR-253) /SDH (G.813) MTIE and TDEV during
reference clock reselection
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
Example I/O Clock Frequency Combinations
Using M2050 Mapper PLL
Base Input
Rate (MHz)
1
625.0000
625.0000
644.5313
Mapper Ratio
Mfec / Rfec
(Pin Selectable)
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
VCSO* and Base
Output Rate
(MHz)
2
644.5313
669.6429
690.5692
33 / 32
15 / 14
15 / 14
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be base rate divided by “Mfin”.
Note 2: Output rate can be base rate divided by “P”.
* Specify VCSO center frequency at time of order.
S
IMPLIFIED
B
LOCK
D
IAGRAM
Loop
Filter
M2050, 51, 52
NBW
LOL
MUX
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
FEC_SEL1:0
FIN_SEL1:0
P_SEL2:0
2
Phase
Detector
0
1
Rfec
Div
VCSO
Mfec Div
Mfec and Rfec
Divider
LUT
Mfin Divider
(1, 4, 5, 25)
P Divider
Mfin Divider
LUT
P Divider
LUT
(1, 4, 5, 25 or TriState)
TriState
FOUT0
nFOUT0
FOUT1
nFOUT1
2
3
Figure 2: Simplified Block Diagram
M2050/51/52 Datasheet Rev 1.0
M2050/51/52 SAW PLL for 10GbE 64b/66b FEC
●
Revised 23Jun2005
Communications Modules
●
Integrated Circuit Systems, Inc.
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Integrated
Circuit
Systems, Inc.
M2050/51/52
SAW PLL
FOR
10G
B
E 64
B
/66
B
FEC
Preliminary Information
P
IN
D
ESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
4
9
5
8
6
7
11, 19, 33
12
13
15
16
17
18
25
20
21
22
23
24
27
28
29
30
31
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
FOUT1
nFOUT1
FOUT0
nFOUT0
P_SEL1
P_SEL0
P_SEL2
nDIF_REF1
DIF_REF1
REF_SEL
nDIF_REF0
DIF_REF0
FIN_SEL1
FIN_SEL0
FEC_SEL0
FEC_SEL1
LOL
I/O
Configuration
Description
Ground
Input
Output
Input
Power
Output
Output
Input
Input
Input
Input
Input
Input
No internal terminator
No internal terminator
Power supply ground connections.
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 8.
Power supply connection, connect to +
3.3
V.
Clock output pair 1. Differential LVPECL.
Clock output pair 0. Differential LVPECL.
, P divider selection. LVCMOS/LVTTL. See Table 7,
Internal pull-down resistor
1
Post-PLL Look-Up Table (LUT), on pg. 4.
P Divider
Biased to Vcc/2
2
Internal pull-down resistor
1
Internal pull-down resistor
1
Biased to Vcc/2
2
Internal pull-down resistor
1
Reference clock input pair 1. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
Reference clock input selection. LVCMOS/LVTTL:
Logic
1
selects
DIF_REF1, nDIF_REF1.
Logic
0
selects
DIF_REF0, nDIF_REF0
.
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
I
nput clock frequency selection. LVCMOS/LVTTL. See
Internal pull-down resistor
1
Table
3
Mfin Divider Look-Up Tables (LUT) on pg. 3.
Mfec and Rfec divider value selection. LVCMOS/ LVTTL.
Internal pull-down resistor
1
See Tables
4
,
5
,and
6
on pg. 3.
Output
32
34, 35, 36
NBW
DNC
Input
Internal pull-UP resistor
1
Do Not Connect.
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase.
3
Logic
1
indicates loss of lock.
Logic
0
indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic
1
- Narrow loop bandwidth
, R
IN
= 2100kΩ.
Logic
0
- Wide bandwidth
, R
IN
= 100kΩ.
Table 2: Pin Descriptions
Note 1: For typical values of internal pull-down and pull-up resistors, see
DC Characteristics
on pg. 10.
Note 2: Biased toVcc/2, with 50kΩ to Vcc and 50kΩ to ground. See
Differential Inputs Biased to VCC/2
in DC Characteristics on pg. 10.
Note 3: See
LVCMOS Output
in DC Characteristics on pg. 10.
M2050/51/52 Datasheet Rev 1.0
Integrated Circuit Systems, Inc.
●
2 of 12
Communications Modules
●
Revised 23Jun2005
w w w. i c s t . c o m
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Integrated
Circuit
Systems, Inc.
M2050/51/52
SAW PLL
FOR
10G
B
E 64
B
/66
B
FEC
Preliminary Information
D
ETAILED
B
LOCK
D
IAGRAM
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
C
LOOP
OP_OUT
R
POST
nOP_OUT
nVC
VC
External
Loop Filter
Components
M2050, 51, 52
NBW
LOL
MUX
Phase
Detector
Rfec
Div
OP_IN
nOP_IN
Hitless Switch Option
Phase Buildout Option
R
IN
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
0
R
IN
1
Loop Filter
Amplifier
Mfin Divider
(1, 4, 5, 25)
Phase
Locked
Loop
(PLL)
SAW Delay Line
Phase
Shifter
VCSO
Mfec Div
FEC_SEL1:0
Mfec/Rfec Divider
LUT
P Divider
(1, 4, 5, 25,
or TriState)
FOUT0
nFOUT0
FOUT1
nFOUT1
FIN_SEL1:0
Mfin Divider
LUT
P Divider
LUT
P_SEL2:0
Figure 3: Detailed Block Diagram
D
IVIDER
S
ELECTION
T
ABLES
Mfin Divider Look-Up Tables (LUT)
The
FIN_SEL1:0
pins select the feedback divider value
(“Mfin”). Since the VCSO frequency is fixed, this allows
input reference selection. The look-up tables vary by
device variant.
M2050/51/52: Mfin Value LUT
Mfin Sample Input Reference Freq. (MHz) Options
FIN_SEL1:0
Value
For
M2050
1
,
M2051
&
M2052
2
Mfec and Rfec Divider Look-Up Tables (LUTs)
The
FEC_SEL
pins select the Mfec/Rfec divider ratio.
The look-up tables vary by device variant. The Mfec
and Rfec values also establish phase detector
frequency. A lower phase detector frequency improves
jitter tolerance and lowers loop bandwidth.
M2050: Map LUT
(10GbE to LAN, 255/238 FEC, or 255/237 FEC)
FEC_SEL1:0
M
fec
R
fec
1 0
Description
Fvcso =
Base Input
Base Output
Rate (MHz)
Rate (MHz)
0
0
1
1
0
1
0
1
25
5
4
1
25.00
125.00
156.25
625.00
Table 3: M2050/51/52: Mfin Value LUT
For
M2050 with Fvcso = 644.5313
(10GbE to 10GbE LAN rate):
0
0
1
1
0
1
0
1
33 32
33 33
15 14
15 15
10GbE
to
10GbE LAN
10GbE LAN repeater
625.0000
644.5313
625.0000
669.6429
644.5313
644.5313
669.6429
669.6429
For
M2050 with Fvcso = 669.6429
(10GbE to 10GbE
255/238
FEC rate):
10GbE
to
10GbE
255/238
FEC
10GbE
255/238
FEC repeater
Note 1: For M2050 with Fvcso = 669.6429
Note 2: For M2051 and M2052 with Fvcso = 625.0000.
For
M2050 with Fvcso = 690.5692
(10GbE LAN to 10GbE LAN
255/238
FEC):
10GbE LAN
to
10GbE LAN
1 0 15 14
255/238
FEC
644.5313 690.5692
1
1
15 15
10GbE LAN
255/238
FEC repeater
690.5692
690.5692
For
M2050 with Fvcso = 693.4830
(10GbE LAN to 10GbE LAN
255/237
FEC):
10GbE LAN
to
10GbE LAN
0 0 85 79
255/237
FEC
644.5313 693.4830
0
1
85 85
10GbE LAN
255/237
FEC repeater
693.4830
693.4830
Table 4: M2050: Map LUT (10GbE to LAN, 255/238 FEC, or 255/237 FEC)
M2050/51/52 Datasheet Rev 1.0
Integrated Circuit Systems, Inc.
●
3 of 12
Communications Modules
●
Revised 23Jun2005
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Integrated
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Systems, Inc.
M2051: De-map LUT
(10GbE LAN or 255/238 FEC to 10GbE)
M2050/51/52
SAW PLL
FOR
10G
B
E 64
B
/66
B
FEC
Preliminary Information
P Divider Look-Up Table (LUT)
The
P_SEL2:0
pins select the P divider values, which set
the output clock frequencies. A P divider of value of
1
will provide a
625.00MHz
output when using a
625.00MHz
VCSO, for example. P divider values of
4
,
5
, or
25
are
also available, plus a TriState mode. The outputs can
be placed into the valid state combinations as listed in
Table 7. (The outputs cannot each be placed into any of
the five available states independently.)
P Value
P_SEL2:0
Use this option to demap from
either
“10GbE LAN”
or
“10GbE 255/238 FEC” encoded to “10GbE”. Also use
this option to operate in 10GbE repeater mode.
The de-mapper FEC PLL ratios (in Table 5) enables
the
M2051-11-625.0000
to accept “base” input
reference frequencies of:
625.00
MHz
(“10GbE”),
644.5313
MHz
(“10GbE
LAN”),
and
669.6429
MHz
(“10GbE
255/238
FEC”).
FEC_SEL1:0
M
fec
R
fec
1 0
Description
Fvcso =
Base Input
Base Output
Rate (MHz)
Rate (MHz)
for
FOUT0
for
FOUT1
25
1
25
4
1
1
4
1
5
5
4
4
5
4
TriState TriState
Output Frequency (MHz)
FOUT0
FOUT1
M2050-625.0000
For
M2051 with Fvcso =
625.00
0
0
1
1
0
1
0
1
32
32
28
14
33
32
30
15
10GbE LAN
to
10GbE
10GbE jitter attenuator
10GbE
255/238
FEC to 10GbE
10GbE
255/238
FEC to 10GbE
644.5313
625.0000
669.6429
669.6429
625.0000
625.0000
625.0000
625.0000
Table 5: M2051: De-map LUT (10GbE LAN or 255/238 FEC to 10GbE)
The Mfec divider value for the first three settings allows
one set of passive filter components to be used for all
three of these modes.
The fourth setting maps “10GbE 255/238 FEC” using
the lowest Mfec value possible. Use this setting to
produce the maximum loop bandwidth.
This option de-maps from
both
“10GbE LAN 255/237
FEC”
and
“10GbE LAN 255/238 FEC” to “10GbE LAN”.
Also use this option to operate in 10GbE LAN repeater
mode.
The de-mapper FEC PLL ratios (in Table 6) enables
the
M2052-11-625.0000
to accept “base” input
reference frequencies of:
644.5313
MHz
(“10GbE
LAN”),
690.5692
MHz
(“10GbE
LAN
255/238
FEC”),
and
693.4830
MHz
(“10GbE
LAN
255/237
FEC”).
FEC_SEL1:0
M
fec
R
fec
1 0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
25.00
25.00
625.00
156.25
125.00
156.25
125.00
N/A
625.00
156.25
625.00
625.00
125.00
156.25
156.25
N/A
Table 7: P Divider Look-Up Table (LUT)
General Guideline for Mfec and Rfec Divider Selection
When
LOL
is to be used for system health monitoring,
the phase detector frequency should be
5MHz
or
greater. Low phase detector frequencies make
LOL
M2052: De-map LUT
(255/237 or 255/238 FEC to 10GbE LAN)
overly sensitive, and higher phase detector frequencies
make
LOL
less sensitive. The
LOL
pin should not be used
during loop timing mode.
F
UNCTIONAL
D
ESCRIPTION
The M2050/51/52 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW delay line provides low jitter
signal performance and establishes the output
frequency of the VCSO (Voltage Controlled SAW
Oscillator). In a given M2050/51/52 device, the VCSO
center frequency is fixed. A common center frequency
is
625.00MHz,
for 10GbE 64b/66b optical network
applications. The VCSO center frequency is specified at
time of order (see “Ordering Information” on pg. 12).
The VCSO has a guaranteed tuning range of
±120
ppm
(commercial temperature grade).
Pin selectable dividers are used within the PLL and
for the output clock. This enables tailoring of device
functionality and performance. The FEC feedback and
reference dividers (the “Mfec Divider” and “Rfec
Divider”) provide the multiplication ratios necessary to
accomodate clock translation for both forward and
inverse Forward Error Correction. The Mfec and Rfec
Description
Fvcso =
Base Input
Base Output
Rate (MHz)
Rate (MHz)
For
M2052
with Fvcso =
625.00
0
0
1
1
0
1
0
1
79
79
84
84
85
79
90
84
10GbE LAN
255/237
FEC to
10GbE LAN
10GbE LAN jitter attenuator
10GbE LAN
255/238
FEC to
10GbE LAN
10GbE LAN jitter attenuator
693.4830
644.5313
690.5692
644.5313
625.0000
625.0000
625.0000
625.0000
Table 6: M2052: De-map LUT (255/237 or 255/238 FEC to 10GbE LAN)
Use this option for multi-rate de-mapping applications
that require one set of PLL passive filter values to
operate over
both
“10GbE LAN 255/237 FEC” and
“10GbE LAN 255/238 FEC”. The Mfec divider value is
kept nearly constant to maintain similar loop bandwidth
using one set of external filter component values.
M2050/51/52 Datasheet Rev 1.0
Integrated Circuit Systems, Inc.
●
4 of 12
Communications Modules
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Revised 23Jun2005
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Systems, Inc.
dividers also control the phase detector frequency. The
feedback divider (labeled “Mfin Divider”) provides the
broader division options needed to accomodate various
reference clock frequencies.
For example, the
M2051-11-625.0000
(see “Ordering
Information”
on pg. 12
)
has a
625.00
MHz VCSO
frequency:
M2050/51/52
SAW PLL
FOR
10G
B
E 64
B
/66
B
FEC
Preliminary Information
Configuration of single-ended input has been facilitated
by biasing
nDIF_REF0
and
nDEF_REF1
to Vcc/2, with 50kΩ
to Vcc and 50kΩ to ground. The input clock structure,
and how it is used with either LVCMOS/LVTTL inputs or
a DC- coupled LVPECL clock, is shown in Figure 4.
•
The de-mapper FEC PLL ratios (in Tables
5
and
6
)
•
enable the
M2051-11-625.0000
to accept “base” input
reference frequencies of:
625.00
MHz
(“10GbE
”
)
,
644.5313
MHz
(“10GbE
LAN
”
)
, and
669.6429
MHz
(“10GbE 255/238
FEC
”
).
The Mfin feedback divider enables the actual input
reference clock to be the base input frequency
divided by
1
,
4
,
5
, or
25
. Therefore, for the base input
frequency of
625.00
MHz, the actual input reference
clock frequencies can be:
625.00
,
156.25
,
125.00
, and
25.00
MHz. (See Table 3 on pg. 3.)
LVCMOS/
LVTTL
50k
Ω
X
VCC
50k
Ω
MUX
0
VCC
127
Ω
50k
Ω
1
LVPECL
82
Ω
VCC
127
Ω
50k
Ω
VCC
50k
Ω
82
Ω
50k
Ω
REF_SEL
Key to Device Variants and Look-up Table Options
Device
Variant
M2050
M2051
M2052
Look-up Table Option
Mfin Lookup Table is:
Mfec Look-up Table is:
Table 4
(mapper LUT)
Table 3
Table 5
(de-mapper LUT)
Table 6
(de-mapper LUT)
Table 8: Key to Device Variants and Look-up Table Options
Figure 4: Input Reference Clocks
Differential Inputs
The M2050/51/52 includes a Loss of Lock (
LOL
)
indicator, which provides status information to system
management software. A Narrow Bandwidth (
NBW
)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
Options are available for Hitless Switching (HS) with or
without Phase Build-out (PBO). Performance conforms
with SONET/ SDH MTIE and TDEV during a reference
clock reselection.
Allowance for a single-ended input has been facilitated
by a unique input resistor bias scheme, which is
described next and shown in Figure 4.
Input Reference Clocks
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the
127
Ω
and
82
Ω
resistors) is ideally suited for both AC and DC
coupled LVPECL reference clock lines. These provide
the
50
Ω
load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(
DIF_REF0
or
DIF_REF1
). The inverting reference input pin
(
nDIF_REF0
or
nDIF_REF1
) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or
nDEF_REF1)
is left floating (not
connected), the input will self-bias at VCC/2.
PLL Operation
The M2050/51/52 is a complete clock PLL. It uses a
phase detector and configurable dividers to
synchronize the output of the VCSO with the selected
reference clock.
The PLL will work correctly, meaning it will phase-lock
the VCSO output to the input reference clock, when the
internal phase detector inputs are able to run at the
same frequency. This means the PLL dividers must be
set appropriately and a suitable reference frequency
must be chosen for the intended output frequency.
When the PLL is not set up appropriately, the VCSO is
M2050/51/52 Datasheet Rev 1.0
Integrated Circuit Systems, Inc.
●
5 of 12
Communications Modules
●
Revised 23Jun2005
w w w. i c s t . c o m
●
tel (508) 852-5400
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