LS830 LS831 LS832 LS833
ULTRA LOW LEAKAGE LOW DRIFT
MONOLITHIC DUAL N-CHANNEL JFET
FEATURES
ULTRA LOW DRIFT
ULTRA LOW NOISE
LOW NOISE
LOW CAPACITANCE
@ 25°C (unless otherwise noted)
Maximum Temperatures
Storage Temperature
Operating Junction Temperature
-55 to +150°C
-55 to +150°C
│ΔV
GS1-2
/ΔT│= 5µV/ºC max.
I
G
=80fA TYP.
e
n
=70nV/√Hz TYP.
C
ISS
=3pf max.
ABSOLUTE MAXIMUM RATINGS NOTE 1
Maximum Voltage and Current for Each Transistor NOTE 1
Gate Voltage to Drain or
-V
GSS
40V
Source
-V
DSO
Drain to Source Voltage
40V
-I
G(f)
-I
G
Gate Forward Current
Gate Reverse Current
10mA
10µA
500mW
SOIC
Top View
TO-71
Top View
Maximum Power Dissipation @ TA = 25ºC
Continuous Power Dissipation (Total)
ELECTRICAL CHARACTERISTICS TA = 25ºC (unless otherwise noted)
SYMBOL
│ΔV
GS1-2
/ΔT│max.
│V
GS1-2
│max.
-I
G
typical
-I
G
typical
I
GSS
typical
I
GSS
typical
CHARACTERISTIC
Drift vs. Temperature
Offset Voltage
Operating
High Temperature
At Full Conduction
High Temperature
LS830 LS831 LS832 LS833 UNITS
5
25
0.1
0.1
0.2
0.5
10
25
0.1
0.1
0.2
0.5
20
25
0.1
0.1
0.2
0.5
75
25
0.5
0.5
1.0
1.0
µV/ºC
mV
pA
nA
pA
nA
TA= +125ºC
V
GS
= 20V, V
GS
= 0V
V
GS
= 0
TA= +125ºC
SYMBOL
BV
GSS
BV
GGO
g
fss
g
fs
│g
fs1-2
/g
fs
│
I
DSS
│I
DSS1-2
/I
DSS
│
CHARACTERISTIC
Breakdown Voltage
Gate-to-Gate Breakdown
TRANSCONDUCTANCE
Full Conduction
Typical Operation
Differential
DRAIN CURRENT
Full Conduction
Differential at Full Conduction
GATE-SOURCE
V
GS
(off)
Cutoff Voltage
-0.6
-2
-4.5
V
V
DS
= 10V
I
D
= 1nA
60
--
400
2
1000
5
µA
%
V
DG
= 10V
V
GS
= 0
70
50
--
300
100
1
500
200
5
µS
µS
%
V
DG
= 10V
V
DG
= 10V
V
GS
= 0
I
D
= 30µA
f = 1kHz
f = 1kHz
MIN.
-40
±40
TYP.
-60
--
MAX.
--
--
UNITS
V
V
CONDITIONS
V
DS
= 0
I
G
= ±1µA
I
G
= -1nA
I
D
= 0
I
S
= 0
V
GS
= 20V
CONDITIONS
V
DG
= 10V
V
DG
= 10V
I
D
= 30µA
I
D
= 30µA
T
A
= -55ºC to +125ºC
Linear Integrated Systems
• 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Doc 201127 06/05/2013 Rev#A5 ECN# LS830 LS831 LS832 LS833
SYMBOL
V
GS
I
GGO
g
OSS
g
OS
│g
OS 1-2
│
CMRR
CMRR
NF
e
n
CHARACTERISTIC
Operating Range
GATE CURRENT
Gate-to-Gate Leakage
OUTPUT CONDUCTANCE
Full Conduction
Operating
Differential
COMMON MODE REJECTION
-20 log │ΔV
GS1-2
/ ΔV
DS
│
-20 log │ΔV
GS1-2
/ ΔV
DS
│
NOISE
Figure
Voltage
CAPACITANCE
MIN.
--
--
--
--
--
--
--
--
--
TYP.
--
1
--
--
--
90
90
--
20
MAX.
-4
--
5
0.5
0.1
--
--
1
70
UNITS
V
pA
µS
µS
µS
dB
dB
dB
CONDITIONS
V
DG
= 10V
V
GG
= ±20V
V
DG
= 10V
V
DG
= 10V
I
D
= 30µA
I
D
= I
S
= 0A
V
GS
= 0
I
D
= 30µA
ΔV
DS
= 10 to 20V
ΔV
DS
= 5 to 10V
V
DS
= 10V
f= 100Hz
V
GS
= 0
NBW= 6Hz
I
D
= 30µA
I
D
=30µA
I
D
=30µA
R
G
=10MΩ
f= 10Hz
nV/√Hz V
DG
= 10V
NBW= 1Hz
C
ISS
C
RSS
C
DD
Input
Reverse Transfer
Drain-to-Drain
--
--
--
--
--
--
3
1.5
0.1
pF
pF
pF
V
DS
= 10V
V
DS
= 10V
V
DG
= 10V
V
GS
= 0
V
GS
= 0
I
D
= 30µA
f= 1MHz
f= 1MHz
0.210
0.170
4
8
NOTES:
1. These ratings are limiting values above which the serviceability of any semiconductor may be impaired
Linear Integrated Systems (LIS) is a 25-year-old, third-generation precision semiconductor company providing
high-quality discrete components. Expertise brought to LIS is based on processes and products developed
at Amelco, Union Carbide, Intersil and Micro Power Systems by company President John H. Hall. Hall,
a protégé of Silicon Valley legend Dr. Jean Hoerni, was the director of IC Development at Union Carbide,
co-founder and vice president of R&D at Intersil, and founder/president of Micro Power Systems.
Linear Integrated Systems
• 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Doc 201127 06/05/2013 Rev#A5 ECN# LS830 LS831 LS832 LS833
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