CMLDM7002A
CMLDM7002AG*
CMLDM7002AJ
SURFACE MOUNT PICOmini
TM
DUAL N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
Central
TM
Semiconductor Corp.
DESCRIPTION:
These CENTRAL SEMICONDUCTOR devices are dual
Enhancement-mode N-Channel Field Effect Transistors,
manufactured by the N-Channel DMOS Process, designed
for high speed pulsed amplifier and driver applications. The
CMLDM7002A utilizes the USA pinout configuration, while
the CMLDM7002AJ utilizes the Japanese pinout
configuration. These devices offer low rDS (ON) and low
VDS(ON).
MARKING CODES: CMLDM7002A:
CMLDM7002AG*:
CMLDM7002AJ:
SYMBOL
VDS
VDG
VGS
ID
IS
IDM
ISM
PD
PD
PD
TJ, Tstg
Θ
JA
60
60
40
280
280
1.5
1.5
350
300
150
-65 to +150
357
SOT-563 CASE
*
Device is
Halogen Free
by design
L02
C2G
02J
UNITS
V
V
V
mA
mA
A
A
mW
mW
mW
°C
°C/W
MAXIMUM RATINGS:
(TA=25°C)
Drain-Source Voltage
Drain-Gate Voltage
Gate-Source Voltage
Continuous Drain Current
Continuous Source Current (Body Diode)
Maximum Pulsed Drain Current
Maximum Pulsed Source Current
Power Dissipation (Note 1)
Power Dissipation (Note 2)
Power Dissipation (Note 3)
Operating and Storage Junction Temperature
Thermal Resistance
ELECTRICAL CHARACTERISTICS PER TRANSISTOR:
(TA=25°C unless otherwise noted)
SYMBOL
TEST CONDITIONS
MIN
MAX
IGSSF, IGSSR
VGS=20V, VDS=0V
100
IDSS
VDS=60V, VGS=0V
1.0
IDSS
VDS=60V, VGS=0V, TJ=125°C
500
ID(ON)
VGS=10V, VDS
≥2.0V
DS(ON)
500
BVDSS
VGS=0V, ID=10μA
60
VGS(th)
VDS=VGS, ID=250μA
1.0
2.5
VDS(ON)
VGS=10V, ID=500mA
1.0
VDS(ON)
VGS=5.0V, ID=50mA
0.15
VGS=0V, IS=400mA
1.2
VSD
rDS(ON)
VGS=10V, ID=500mA
2.0
rDS(ON)
VGS=10V, ID=500mA, TJ=125°C
3.5
rDS(ON)
VGS=5.0V, ID=50mA
3.0
rDS(ON)
VGS=5.0V, ID=50mA, TJ=125°C
5.0
gFS
VDS
≥2V
DS(ON), ID=200mA
80
Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0 mm
2
(2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0 mm
2
(3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4 mm
2
UNITS
nA
μA
μA
mA
V
V
V
V
V
Ω
Ω
Ω
Ω
mS
R4 (8-January 2009)
Central
TM
Semiconductor Corp.
CMLDM7002A
CMLDM7002AG*
CMLDM7002AJ
SURFACE MOUNT PICOmini
TM
DUAL N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
ELECTRICAL CHARACTERISTICS PER TRANSISTOR - Continued:
(TA=25°C unless otherwise noted)
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
Crss
VDS=25V, VGS=0, f=1.0MHz
5.0
pF
Ciss
VDS=25V, VGS=0, f=1.0MHz
50
pF
Coss
VDS=25V, VGS=0, f=1.0MHz
25
pF
ton / toff
VDD=30V, VGS=10V, ID=200mA
20
ns
RG=25Ω, RL=150Ω
SOT-563 CASE - MECHANICAL OUTLINE
PIN CONFIGURATIONS
CMLDM7002A
(USA Pinout)
CMLDM7002AG*
CMLDM7002AJ
(Japanese Pinout)
LEAD CODE:
1) GATE Q1
2) SOURCE Q1
3) DRAIN Q2
4) GATE Q2
5) SOURCE Q2
6) DRAIN Q1
MARKING CODES: CMLDM7002A: L02
CMLDM7002AG*: C2G
*
Device is
Halogen Free
by design
LEAD CODE:
1) SOURCE Q1
2) GATE Q1
3) DRAIN Q2
4) SOURCE Q2
5) GATE Q2
6) DRAIN Q1
MARKING CODE: 02J
R4 (8-January 2009)