530KA1213M00DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530KA1213M00DG

530KA1213M00DG: DescriptionCMOS/TTL Output Clock Oscillator, 1213MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530KA1213M00DG Overview

CMOS/TTL Output Clock Oscillator, 1213MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530KA1213M00DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	1213 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

STK1060 power amplifier circuit diagram

Timing socket principle circuit diagram

Simple medium wave radio circuit using varactor diode and linear op amp

watchdog circuit

555 light controlled strobe security light circuit

Motor overheating verbal alarm circuit

What is the difference between computer organization principles and computer architecture?: I have already learned the principles of computer organization, and next semester I will take the course of computer architecture. I wonder how big the difference is between the two? Can you give me s...; Cathy Embedded System

CircuitPython 6.0.0 Alpha 1 released: From: https://blog.adafruit.com/2020/07/03/ci ... -released/This is the first Alpha release of CircuitPython 6.0.0. It is a renumbered version of 5.4.0 as the i2cslave module and class have been renam...; dcexpert MicroPython Open Source section

Timing charger made by single chip microcomputer (schematic diagram + source code): [color=#000000][font=微软雅黑, Tahoma,]Timed charger[/font][backcolor=rgb(247, 247, 247)][font=微软雅黑, Tahoma,]Working principle: The timed charger consists of two 220V to 5V power modules, one for the sing...; cardin6 Creative Market

[Hua Diao Experience] 19 Hezhou ESP32_C3 lights up WS2812B hard screen: I have a 64-bit and a 256-bit WS2812B hard screen, and now I try to light them up....; eagler8 DIY/Open Source Hardware

Rules for drawing circuit diagrams: [color=#666666][font=Helvetica, Tahoma, Arial, sans-serif][size=12px]Circuit diagram drawing rules. In order to enable the viewer to correctly and conveniently understand the entire content of the cir...; qwqwqw2088 PCB Design

【CN0179】Low Noise 12 GHz Microwave Fractional-N Phase-Locked Loop (PLL) Using Active Loop Filter and RF: Circuit Functionality and Benefits4 mA to 20 mA current loop transmitter for communication between process control systems and their actuators. In addition to being cost-effective, this circuit is the...; EEWORLD社区 ADI Reference Circuit

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components