530RA1349M00DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530RA1349M00DG

530RA1349M00DG: DescriptionLVPECL Output Clock Oscillator, 1349MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530RA1349M00DG Overview

LVPECL Output Clock Oscillator, 1349MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530RA1349M00DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	1349 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Negative voltage generator circuit, NE555 charge pump

Functional block diagram of MC1428

Two-channel audio signal conditioning circuit

Single Supply Low Voltage Band Pass Filter Amplifier

Hum filter circuit diagram

It seems like a very difficult question. Can C language printf control the total length of double output?: I feel this is a very difficult problem, and sprintf may not be able to implement it. For example, if you want to output a total length of 4 digits (excluding the decimal point, but including the nega...; littleshrimp MCU

Array-like assignment in fpga: Hello everyone, I am doing an LCD1602 display experiment using a Spartan 3e development board. I want to use Verilog to write an array. At the beginning, I set the initial value of this array, and the...; hujn FPGA/CPLD

Please help me with the data selector issue: [align=left][color=#000][b]SN74LVC157APW is a four-way data selector/multiplexer[/b][/color][/align][align=left][color=#000][b]I want to find four single-way ones. What model can I use to replace them...; fengye Analogue and Mixed Signal

I am a Java programmer. What basic knowledge do I need to enter the field of embedded development?: I am a Java programmer. What basic knowledge do I need to enter the field of embedded development?...; comnet001 Embedded System

Apply for LM3S8962 evaluation board to make a small thing: There are already ready-made modules: car body, sensor group, wireless communication module, motor drive module, battery pack, etc.Required module: LM3S8962 evaluation boardThe phone photo is a bit ba...; 某某人 Microcontroller MCU

Design of solar cell phone charger based on 51 single chip microcomputer: Solar energy isan attractive energy source for powering portable devices. For some time, it has been widely used in applications such as calculators and space shuttles. Recently, solar energy is being...; twiky0 Energy Infrastructure?

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components