Intel
®
Xeon
®
Processor 5500 Series
Datasheet, Volume 2
April 2009
Order Number: 321322-002
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2
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2
C bus/protocol and was developed
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Copyright © 2009, Intel Corporation.
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Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
Contents
1
Introduction
............................................................................................................ 15
1.1
Terminology ..................................................................................................... 15
1.1.1
Processor Terminology .......................................................................... 15
1.2
References ....................................................................................................... 17
Register Description
................................................................................................ 19
2.1
Register Terminology ......................................................................................... 19
2.2
Platform Configuration Structure ......................................................................... 20
2.3
Device Mapping................................................................................................. 21
2.4
Detailed Configuration Space Maps ...................................................................... 23
2.5
PCI Standard Registers ...................................................................................... 45
2.5.1
VID - Vendor Identification Register ........................................................ 45
2.5.2
DID - Device Identification Register......................................................... 45
2.5.3
RID - Revision Identification Register....................................................... 46
2.5.4
CCR - Class Code Register ..................................................................... 46
2.5.5
HDR - Header Type Register................................................................... 47
2.5.6
SID/SVID - Subsystem Identity/Subsystem Vendor
Identification Register ........................................................................... 47
2.5.7
PCICMD - Command Register ................................................................. 48
2.5.8
PCISTS - PCI Status Register.................................................................. 49
2.6
Generic Non-core Registers ................................................................................ 50
2.6.1
MAXREQUEST_LC ................................................................................. 50
2.6.2
MAXREQUEST_LS ................................................................................. 51
2.6.3
MAXREQUEST_LL.................................................................................. 51
2.6.4
MAX_RTIDS ......................................................................................... 51
2.6.5
DESIRED_CORES .................................................................................. 52
2.6.6
MEMLOCK_STATUS ............................................................................... 52
2.6.7
MC_CFG_CONTROL ............................................................................... 53
2.6.8
POWER_CNTRL_ERR_STATUS................................................................. 53
2.6.9
CURRENT_UCLK_RATIO ......................................................................... 54
2.6.10 MIRROR_PORT_CTL .............................................................................. 55
2.6.11 MIP_PH_CTR_L0
MIP_PH_CTR_L1 ................................................................................... 55
2.6.12 MIP_PH_PRT_L0
MIP_PH_PRT_L1 ................................................................................... 56
2.7
SAD - System Address Decoder Registers ............................................................. 56
2.7.1
SAD_PAM0123 ..................................................................................... 56
2.7.2
SAD_PAM456 ....................................................................................... 58
2.7.3
SAD_HEN ............................................................................................ 59
2.7.4
SAD_SMRAM ........................................................................................ 59
2.7.5
SAD_PCIEXBAR .................................................................................... 60
2.7.6
SAD_DRAM_RULE_0
SAD_DRAM_RULE_1
SAD_DRAM_RULE_2
SAD_DRAM_RULE_3
SAD_DRAM_RULE_4
SAD_DRAM_RULE_5
SAD_DRAM_RULE_6
SAD_DRAM_RULE_7.............................................................................. 60
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Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
3
2.8
2.9
2.10
2.11
SAD_INTERLEAVE_LIST_0
SAD_INTERLEAVE_LIST_1
SAD_INTERLEAVE_LIST_2
SAD_INTERLEAVE_LIST_3
SAD_INTERLEAVE_LIST_4
SAD_INTERLEAVE_LIST_5
SAD_INTERLEAVE_LIST_6
SAD_INTERLEAVE_LIST_7 ......................................................................61
Intel QPI Link Registers ......................................................................................61
2.8.1
QPI_QPILCP_L0
QPI_QPILCP_L1 ....................................................................................61
2.8.2
QPI_QPILCL_L0
QPI_QPILCL_L1.....................................................................................62
2.8.3
QPI_QPILS_L0
QPI_QPILS_L1 ......................................................................................63
2.8.4
QPI_DEF_RMT_VN_CREDITS_L0
QPI_DEF_RMT_VN_CREDITS_L1..............................................................63
2.8.5
QPI_RMT_QPILP0_STAT_L0
QPI_RMT_QPILP0_STAT_L1 ....................................................................63
2.8.6
QPI_RMT_QPILP1_STAT_L0
QPI_RMT_QPILP1_STAT_L1 ....................................................................64
2.8.7
QPI_RMT_QPILP2_STAT_L0
QPI_RMT_QPILP2_STAT_L1 ....................................................................64
2.8.8
QPI_RMT_QPILP3_STAT_L0
QPI_RMT_QPILP3_STAT_L1 ....................................................................65
Intel QPI Physical Layer Registers ........................................................................66
2.9.1
QPI_0_PH_CPR
QPI_1_PH_CPR .....................................................................................66
2.9.2
QPI_0_PH_CTR
QPI_1_PH_CTR .....................................................................................67
2.9.3
QPI_0_PH_PIS
QPI_1_PH_PIS ......................................................................................68
2.9.4
QPI_0_PH_PTV
QPI_1_PH_PTV .....................................................................................69
2.9.5
QPI_0_PH_LDC
QPI_1_PH_LDC .....................................................................................69
2.9.6
QPI_0_PH_PRT
QPI_1_PH_PRT .....................................................................................70
2.9.7
QPI_0_PH_PMR0
QPI_1_PH_PMR0 ...................................................................................70
2.9.8
QPI_0_EP_SR
QPI_1_EP_SR .......................................................................................71
2.9.9
QPI_0_EP_MCTR
QPI_1_EP_MCTR ...................................................................................71
Intel QPI Miscellaneous Registers .........................................................................72
2.10.1 QPI_0_PLL_STATUS
QPI_1_PLL_STATUS...............................................................................72
2.10.2 QPI_0_PLL_RATIO
QPI_1_PLL_RATIO .................................................................................72
Integrated Memory Controller Control Registers .....................................................73
2.11.1 MC_CONTROL .......................................................................................73
2.11.2 MC_STATUS .........................................................................................74
2.11.3 MC_SMI_DIMM_ERROR_STATUS .............................................................74
2.11.4 MC_SMI_CNTRL ....................................................................................75
2.11.5 MC_RESET_CONTROL ............................................................................76
2.11.6 MC_CHANNEL_MAPPER ..........................................................................76
2.11.7 MC_MAX_DOD ......................................................................................77
2.11.8 MC_RD_CRDT_INIT ...............................................................................77
2.11.9 MC_CRDT_WR_THLD .............................................................................78
2.7.7
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Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
2.12
2.13
2.14
2.15
2.11.10 MC_SCRUBADDR_LO ............................................................................. 79
2.11.11 MC_SCRUBADDR_HI ............................................................................. 79
TAD - Target Address Decoder Registers .............................................................. 80
2.12.1 TAD_DRAM_RULE_0
TAD_DRAM_RULE_1
TAD_DRAM_RULE_2
TAD_DRAM_RULE_3
TAD_DRAM_RULE_4
TAD_DRAM_RULE_5
TAD_DRAM_RULE_6
TAD_DRAM_RULE_7.............................................................................. 80
2.12.2 TAD_INTERLEAVE_LIST_0
TAD_INTERLEAVE_LIST_1
TAD_INTERLEAVE_LIST_2
TAD_INTERLEAVE_LIST_3
TAD_INTERLEAVE_LIST_4
TAD_INTERLEAVE_LIST_5
TAD_INTERLEAVE_LIST_6
TAD_INTERLEAVE_LIST_7...................................................................... 81
Integrated Memory Controller RAS Registers ......................................................... 82
2.13.1 MC_SSRCONTROL................................................................................. 82
2.13.2 MC_SCRUB_CONTROL ........................................................................... 83
2.13.3 MC_RAS_ENABLES................................................................................ 83
2.13.4 MC_RAS_STATUS ................................................................................. 83
2.13.5 MC_SSRSTATUS ................................................................................... 84
2.13.6 MC_COR_ECC_CNT_0
MC_COR_ECC_CNT_1
MC_COR_ECC_CNT_2
MC_COR_ECC_CNT_3
MC_COR_ECC_CNT_4
MC_COR_ECC_CNT_5............................................................................ 84
Integrated Memory Controller Test Registers......................................................... 85
2.14.1 MC_TEST_ERR_RCV1 ............................................................................ 85
2.14.2 MC_TEST_ERR_RCV0 ............................................................................ 85
2.14.3 MC_TEST_PH_CTR ................................................................................ 86
2.14.4 MC_TEST_PH_PIS ................................................................................. 86
2.14.5 MC_TEST_PAT_GCTR ............................................................................ 86
2.14.6 MC_TEST_PAT_BA ................................................................................ 87
2.14.7 MC_TEST_PAT_IS ................................................................................. 87
2.14.8 MC_TEST_PAT_DCD .............................................................................. 87
Integrated Memory Controller Channel Control Registers ........................................ 88
2.15.1 MC_CHANNEL_0_DIMM_RESET_CMD
MC_CHANNEL_1_DIMM_RESET_CMD
MC_CHANNEL_2_DIMM_RESET_CMD....................................................... 88
2.15.2 MC_CHANNEL_0_DIMM_INIT_CMD
MC_CHANNEL_1_DIMM_INIT_CMD
MC_CHANNEL_2_DIMM_INIT_CMD.......................................................... 88
2.15.3 MC_CHANNEL_0_DIMM_INIT_PARAMS
MC_CHANNEL_1_DIMM_INIT_PARAMS
MC_CHANNEL_2_DIMM_INIT_PARAMS .................................................... 89
2.15.4 MC_CHANNEL_0_DIMM_INIT_STATUS
MC_CHANNEL_1_DIMM_INIT_STATUS
MC_CHANNEL_2_DIMM_INIT_STATUS ..................................................... 91
2.15.5 MC_CHANNEL_0_DDR3CMD
MC_CHANNEL_1_DDR3CMD
MC_CHANNEL_2_DDR3CMD ................................................................... 92
2.15.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT
MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT
MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT...................................... 93
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
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