530KB1380M00DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 530KB1380M00DGR

530KB1380M00DGR: DescriptionCMOS/TTL Output Clock Oscillator, 1380MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530KB1380M00DGR Overview

CMOS/TTL Output Clock Oscillator, 1380MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530KB1380M00DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	1380 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Schematic diagram of receiving control principle

Two basic circuits of photorelay c

Electronic switching preamplifier

DC boost module AH812 application circuit

Temperature measuring circuit with distance transmitter

OPT301 integrated diode and operational amplifier circuit

SensorTile principle and composition: 1. SensorTile is a unique integrated development platform. Compared with other separate components, it requires at least 3 expansion boards to achieve similar functions.The matching components are as ...; fyaocn MEMS sensors

I can't help but speak out: I have been working for almost a year. I am doing R&D and the girl next to me is doing testing. I am so busy all day long, while the girl next to me is so idle. She is always browsing the campus webpa...; hangzhoucainiao Talking

Can you please advise on the design of AC voltage data acquisition module? ? Urgent!!: I want to collect 380V AC voltage, and I use TAV14 voltage transformer, which can convert 380V AC voltage into a small signal of -2.4V~+2.4V, and then amplify it twice and directly pass it to AD574; T...; hahazhenxin Embedded System

How is the value of d_buf set? ? ? ? ?: void handle(void) { uint y; if(f_d12) { if(!F_S1) isv=0; else isv=1; if(!isv) { if(!F_S4) d_buf[8]=0x8a; else d_buf[8 ]=0x0a; y=fcnt; if(y<1000) { d_buf[9]=0x13; d_buf[10]=0x13; d_buf[11]=y/100; y=y%1...; panshiowen Embedded System

Class D Amplifier Design Example: Data introduction: Using switching mode to achieve low-frequency power amplification (i.e. Class D amplification) is to improve efficiency http://www.cndzz.com/user/show/1444.htm...; maker Analog electronics

μC/OS-II Lecture Courseware PPT: Share some information, hope it will be helpful to everyone! :) There is a very clean and concise ucos ii porting template!! (it has been ported on lm3s8962)[[i]This post was last edited by Panda on 2...; 熊猫 Real-time operating system RTOS

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components