EEWORLDEEWORLDEEWORLD

Part Number

Search

530SC771M000DGR

Description
LVDS Output Clock Oscillator, 771MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

530SC771M000DGR Overview

LVDS Output Clock Oscillator, 771MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530SC771M000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability7%
JESD-609 codee4
Manufacturer's serial number530
Installation featuresSURFACE MOUNT
Nominal operating frequency771 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVDS
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Problems with installing wince5.0
I just installed wince5.0. When I opened platform builder 5.0, two prompt boxes popped up, one was: No primary processors are available. The build system will be disabled, It is likely that a build sy...
yll2008wd Embedded System
Live Q&A Record: High Efficiency and Small Size Bidirectional DC-DC Converter Design, March 30, 2017
[font=微软雅黑][size=3]Live broadcast date: March 30, 2017 Topic: High-efficiency and small-size bidirectional DC-DC converter design Replay: [url=https://training.eeworld.com.cn/TI/video/9142]https://tra...
EE大学堂 TI Technology Forum
When will RT-Thread release an updated programming guide?
The introduction to version 0.3 is a bit general. When will a more detailed explanation be available?...
houfire007 Embedded System
How much time does it take between these two instructions?
If SYS_CLK is 72M and PCLK2=36M, how long does it take to callGPIO_SetBits(GPIOB,GPIO_pin_1);GPIO_ResetBits(GPIOB,GPIO_pin_1);these two library functions?...
socvince stm32/stm8
High difficulty problem, insufficient code space
Our program is based on a CPU design with a built-in 512KB FLASH ROM from NXP. Now we find that the program space is not enough to fix bugs and add new functions. We have done some work on code optimi...
frankie17 Embedded System
Let's talk about the most disappointing company we have ever encountered.
The first company I joined right after graduation was a huge pit:surrender: I basically had to work overtime until nine o'clock every day, and I had to go to work on Sundays if I had something to do, ...
天天1 Talking

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1164  2206  1786  2342  2612  24  45  36  48  53 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号