531BB673M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531BB673M000DGR

531BB673M000DGR: DescriptionLVDS Output Clock Oscillator, 673MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531BB673M000DGR Overview

LVDS Output Clock Oscillator, 673MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531BB673M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	673 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Resistance furnace thyristor temperature control circuit 2

One of the heavy load starting thermal relay protection circuits

TA7241AP audio IC circuit diagram

Flash doorbell circuit

555 single-phase thyristor zero-crossing trigger electric furnace temperature control device circuit

Current control circuit using power amplifier as differential amplifier

Is there a competition tomorrow? Anyone who knows please help me with the questions!: [i=s]This post was last edited by paulhyde on 2014-9-15 09:15[/i]I have a competition tomorrow. Anyone with questions can help me with the questions! I’m afraid the network is not good! Anyone who has...; yangyi1818 Electronics Design Contest

Transfer a good article to learn Verilog: [font=楷体_GB2312][color=royalblue]Specifications are very important[/color][/font] [font=楷体_GB2312][color=royalblue] Friends who have worked in the company must know that the company emphasizes specifi...; 歹匕示申 FPGA/CPLD

[Analog Electronics Elective Test] + Amplifier Bandwidth: I didn't really understand the meaning of bandwidth before, but after reading this, I finally understood it a little. Our books all say "virtual short and virtual disconnection" is enough, but actual ...; 吾妻思萌 TI Technology Forum

Review summary: Mir Allwinner automotive-grade CPU development board MYC-YT507: Activity details: [Mil Allwinner automotive-grade CPU development board MYC-YT507]Updated to 2022-08-07Evaluation report summary:@lugl4313820[Mill MYB-YT507 development board trial experience] Python ...; EEWORLD社区 Special Edition for Assessment Centres

How to batch modify pads in PCB design protel?: How to modify PCB pads in batches? The modification methods in DXF or 99SE, PADS software are roughly the same. Take PCB design Protel 99se as an example: Double-click the pad to be modified. If you w...; ESD技术咨询 PCB Design

Xiaomi Bluetooth mouse with touch power control: [b][color=#ff0000]This content is originally created by EEWORLD forum user [size=3]dcexpert[/size]. If you want to reprint or use it for commercial purposes, you must obtain the author's consent and i...; dcexpert DIY/Open Source Hardware

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components