EEWORLDEEWORLDEEWORLD

Part Number

Search

530MB85M0000DGR

Description
LVPECL Output Clock Oscillator, 85MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

530MB85M0000DGR Overview

LVPECL Output Clock Oscillator, 85MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530MB85M0000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Manufacturer's serial number530
Installation featuresSURFACE MOUNT
Nominal operating frequency85 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
pci9054 cannot be adjusted. I wonder if it is due to FPGA timing delay.
The company has a mature architecture, but it has problems for me. Originally, LCLK was directly given by an external crystal oscillator. I entered the FPGA and then gave the 9054 chip through the FPG...
流浪的猥琐 FPGA/CPLD
Here is a picture that explains one of the frequency band uses I shared before.
Millimeter waves usually refer to electromagnetic waves with a frequency band of 30~300GHz and a corresponding wavelength of 1~10mm. The operating frequency is between microwaves and far infrared wave...
btty038 RF/Wirelessly
[Problem Feedback] Anlu TangDynasty ChipWatcher clock source selection problem
As far as I understand, ChipWatcher should only allow one clock source to be selected. However, in actual use, it seems that even after selecting multiple ones, there is only one in the end. In this c...
littleshrimp FPGA/CPLD
Please help me~~a small program for intel8051
Store 20 data consecutively at RAM30H, move them to 50H, store and count the total number of 05H in the data block. How to do it in assembly~~Thanks for your advice~~...
mingboal Embedded System
I got my SensorTag, here are some pictures to show you
[align=center][b][size=7]I got my SensorTag, here are some pictures for demonstration[/size][/b][/align] [b]The sad thing is that there is no phone that supports 4.0: ([/b] [atta ch]137765[/attach]...
在路上的旁观者 Wireless Connectivity
Risky Phenomena in FPGAs
When a signal passes through the wires and logic units inside the FPGA device, there is a certain delay. The size of the delay is related to the length of the wires and the number of logic units, and ...
eeleader FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2506  2380  1449  1149  2056  51  48  30  24  42 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号