531JA98M0000BGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531JA98M0000BGR

531JA98M0000BGR: DescriptionCMOS Output Clock Oscillator, 98MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size268KB，15 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531JA98M0000BGR Overview

CMOS Output Clock Oscillator, 98MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531JA98M0000BGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TAPE AND REEL
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	98 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS
physical size	7.0mm x 5.0mm x 1.85mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.0 7/06

Si530/531

Recommended Resources

Multi-channel pulse encoder

SH-803 Holiday Lights ASIC

Power capacitor compensation protector circuit

Manual forward control circuit

Three-tube astable trigger triac circuit

Single junction transistor voltage dividing ratio measurement circuit

Comprehensive understanding of logic analyzer (Part 1): [p=16, null, left][color=rgb(0, 0, 0)][font=Arial, Helvetica, sans-serif, 宋体][size=12px]For many applications, modern logic analyzers can get to the root cause of a problem in less time than other ins...; wstt Integrated technical exchanges

Newbie help! Regarding the issue of lcd12864 (with font library), I hope everyone can help!: After burning the program, I don't know what went wrong with the program, and the picture can't be displayed! ? The microprocessor uses STC89c52RC. Attached is the source code, and I hope the veterans...; 迈步xxzj 51mcu

Complete power supply design at your fingertips! WEBENCH Power Designer design tool: [b][size=3]The WEBENCH design environment provides you with the comprehensive design and prototyping tools you need to create a power supply or DC/DC converter that can effectively meet your design re...; qwqwqw2088 Analogue and Mixed Signal

A very cool and practical oscilloscope touch interface, would you choose it?: [font="][size=10.5pt] [/size][/font][font=宋体][size=10.5pt]Smartphones have become standard with full touch screens, but this is my first time to experience a full touch screen oscilloscope. A few days...; 杜拉是只狗 Test/Measurement

Analyzing intermodulation distortion factors to consider when designing ADCs: Intermodulation distortion (IMD) is a common measure of linearity in amplifiers, gain blocks, mixers, and other RF components. Second- and third-order intercept points (IP2 and IP3) are the figures of...; Jacktang Analogue and Mixed Signal

Nexperia ESD Webinar Invitation: Nexperia sincerely invites you to participate in the Nexperia ESD Electronic Design Engineer Technical Seminar, which will be held online on September 22!Seminar time: 2020-9-22 2:00-3:30 PMThis semin...; eric_wang Integrated technical exchanges

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components