IS61LPS25636A-200B2I datasheet, PDF

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IS61LPS25636A-200B2I: DescriptionCache SRAM, 256KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119; Categorystorage storage; File Size1010KB，35 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61LPS25636A-200B2I Overview

Cache SRAM, 256KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119

IS61LPS25636A-200B2I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Factory Lead Time	10 weeks
Maximum access time	3.1 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	9437184 bit
Memory IC Type	CACHE SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	2.41 mm
Maximum standby current	0.105 A
Minimum standby current	3.14 V
Maximum slew rate	0.275 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,

IS61VPS51218A, IS61VPS25636A

256K x 36, 256K x 32, 512K x 18

9 Mb SYNCHRONOUS PIPELINED,

SINgLE CYCLE DESELECT STATIC RAM

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth ex-

pansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for BGA package

• Power Supply

LPS: V

3.3V + 5%,

ddq

3.3V/2.5V + 5%

VPS: V

2.5V + 5%,

ddq

2.5V + 5%

• JEDEC 100-Pin QFP, 119-ball BGA, and 165-

ball BGA packages

• Lead-free available

JUNE

2015

IS64LPS25636A and IS61LPS/VPS51218A are high-

speed, low-power synchronous static RAMs

designed

to provide burstable,

high-performance

memory for com-

munication and networking applications. The IS61LPS/

VPS25636A and IS64LPS25636A are organized as

262,144 words by 36 bits. The IS61LPS25632A

organized as 262,144 words by 32 bits. The IS61LPS/

VPS51218A is organized as 524,288 words by 18 bits.

Fabricated with

ISSI

's advanced CMOS technology,

the device integrates a 2-bit burst counter, high-speed

SRAM core, and high-drive capability outputs into a single

monolithic circuit. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single

clock input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be

one to four bytes wide as controlled by the write control

inputs.

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte

write enable (BWE) input combined with one or more

individual byte write signals (BWx).

In addition, Global

Write (GW)

is available for writing all bytes at one time,

regardless of the byte write controls.

Bursts can be initiated with either ADSP

(Address Status

Processor) or ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence or-

der, Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH

or left floating.

DESCRIPTION

The

ISSI

IS61LPS/VPS25636A, IS61LPS25632A,

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

250

2.6

250

200

3.1

200

166

3.5

166

Units

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc.

Rev.

05/25/2015

IS61LPS25636A-200B2I Related Products

	IS61LPS25636A-200B2I	IS61LPS25636A-200TQLI	IS61LPS51218A-200TQLI	IS64LPS25636A-166TQLA3	IS64LPS25636A-166TQLA3-TR	IS61LPS25636A-200B3I	IS61LPS25636A-200B3LI	IS61LPS25636A-200TQ2LI	IS61LPS25636A-200TQI-TR	IS61LPS51218A-200TQI
Description	Cache SRAM, 256KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119	Cache SRAM, 256KX36, 3.1ns, CMOS, PQFP100, LEAD FREE, TQFP-100	Cache SRAM, 512KX18, 3.1ns, CMOS, PQFP100, LEAD FREE, TQFP-100	Cache SRAM, 256KX36, 3.8ns, CMOS, PQFP100, TQFP-100	IC SRAM 9MBIT 166MHZ 100TQFP	Cache SRAM, 256KX36, 3.1ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165	Cache SRAM, 256KX36, 3.1ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-165	Cache SRAM, 256KX36, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, LQFP-100	256KX36 CACHE SRAM, 3.1ns, PQFP100, TQFP-100	512KX18 CACHE SRAM, 3.1ns, PQFP100, TQFP-100
package instruction	BGA, BGA119,7X17,50	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP,	TBGA, BGA165,11X15,40	TBGA, BGA165,11X15,40	LQFP,	TQFP-100	TQFP-100
Reach Compliance Code	compliant	compli	compliant	compliant	unknown	compliant	compliant	compliant	compliant	compliant
Maximum access time	3.1 ns	3.1 ns	3.1 ns	3.8 ns	3.8 ns	3.1 ns	3.1 ns	3.1 ns	3.1 ns	3.1 ns
JESD-30 code	R-PBGA-B119	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PBGA-B165	R-PBGA-B165	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
length	22 mm	20 mm	20 mm	20 mm	20 mm	15 mm	15 mm	20 mm	20 mm	20 mm
memory density	9437184 bit	9437184 bi	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit
Memory IC Type	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
memory width	36	36	18	36	36	36	36	36	36	18
Number of functions	1	1	1	1	1	1	1	1	1	1
Number of terminals	119	100	100	100	100	165	165	100	100	100
word count	262144 words	262144 words	524288 words	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words	524288 words
character code	256000	256000	512000	256000	256000	256000	256000	256000	256000	512000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	125 °C	125 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
organize	256KX36	256KX36	512KX18	256KX36	256KX36	256KX36	256KX36	256KX36	256KX36	512KX18
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	LQFP	LQFP	LQFP	LQFP	TBGA	TBGA	LQFP	LQFP	LQFP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Maximum seat height	2.41 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.2 mm	1.2 mm	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.165 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	AUTOMOTIVE	AUTOMOTIVE	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	GULL WING	GULL WING	GULL WING	GULL WING	BALL	BALL	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	1 mm	1 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	BOTTOM	QUAD	QUAD	QUAD	QUAD	BOTTOM	BOTTOM	QUAD	QUAD	QUAD
width	14 mm	14 mm	14 mm	14 mm	14 mm	13 mm	13 mm	14 mm	14 mm	14 mm
Is it lead-free?	Contains lead	Lead free	Lead free	Lead free	-	Contains lead	Lead free	-	Contains lead	Contains lead
Is it Rohs certified?	incompatible	conform to	conform to	conform to	-	incompatible	conform to	conform to	incompatible	incompatible
Maker	Integrated Silicon Solution ( ISSI )	-	-	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	-	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA	QFP	QFP	QFP	-	BGA	BGA	-	QFP	QFP
Contacts	119	100	100	100	-	165	165	-	100	100
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	-	3A991.B.2.A	3A991.B.2.A	-	3A991.B.2.A	3A991.B.2.A
Factory Lead Time	10 weeks	10 weeks	10 weeks	12 weeks	12 weeks	-	10 weeks	10 weeks	12 weeks	12 weeks
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	-	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	200 MHz	200 MHz	200 MHz	166 MHz	-	200 MHz	200 MHz	-	-	200 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	-	COMMON	COMMON	-	-	COMMON
JESD-609 code	e0	e3	e3	e3	-	e0	e1	-	e0	e0
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	-	3-STATE	3-STATE	-	-	3-STATE
Encapsulate equivalent code	BGA119,7X17,50	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	-	BGA165,11X15,40	BGA165,11X15,40	-	-	QFP100,.63X.87
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	260	260	260	-	NOT SPECIFIED	260	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	-	2.5/3.3,3.3 V	2.5/3.3,3.3 V	-	-	2.5/3.3,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified
Maximum standby current	0.105 A	0.105 A	0.105 A	0.13 A	-	0.105 A	0.105 A	-	-	0.105 A
Minimum standby current	3.14 V	3.14 V	3.14 V	3.14 V	-	3.14 V	3.14 V	-	-	3.14 V
Maximum slew rate	0.275 mA	0.275 mA	0.275 mA	0.3 mA	-	0.275 mA	0.275 mA	-	-	0.275 mA
Terminal surface	Tin/Lead (Sn/Pb)	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	-	Tin/Lead (Sn/Pb)	Tin/Silver/Copper (Sn/Ag/Cu)	-	TIN LEAD	Tin/Lead (Sn/Pb)
Maximum time at peak reflow temperature	NOT SPECIFIED	10	40	40	-	NOT SPECIFIED	40	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Base Number Matches	-	1	1	1	1	1	1	1	1	-

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