K4T1G044QQ
K4T1G084QQ
DDR2 1.55V SDRAM
1Gb Q-die DDR2 1.55V SDRAM Specification
60FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.2 December 2008
K4T1G044QQ
K4T1G084QQ
DDR2 1.55V SDRAM
Table of Contents
1.0 Ordering Information ................................................................................................................... 4
2.0 Key Features ................................................................................................................................ 4
3.0 Package Pinout/Mechanical Dimension & Addressing ............................................................ 5
3.1 x4 package pinout (Top View) : 60ball FBGA Package
..................................................................... 5
3.2 x8 package pinout (Top View) : 60ball FBGA Package
..................................................................... 6
3.3 FBGA Package Dimension (x4/x8)
................................................................................................. 7
4.0 Input/Output Functional Description ......................................................................................... 8
5.0 DDR2 SDRAM Addressing .......................................................................................................... 9
6.0 Absolute Maximum DC Ratings ................................................................................................ 10
7.0 AC & DC Operating Conditions ................................................................................................ 10
7.1 Recommended DC Operating Conditions (SSTL - 1.8)
................................................................... 10
7.2 Operating Temperature Condition
............................................................................................... 11
7.3 Input DC Logic Level
................................................................................................................. 11
................................................................................................................. 11
7.5 AC Input Test Conditions
........................................................................................................... 11
7.6 Differential input AC logic Level
................................................................................................. 12
7.7 Differential AC output parameters
............................................................................................... 12
8.0 ODT DC electrical characteristics ............................................................................................ 12
9.0 IDD Specification Parameters and Test Conditions ............................................................... 13
10.0 DDR2 SDRAM IDD Spec Table ................................................................................................ 15
11.0 Input/Output capacitance ........................................................................................................ 16
12.0 Electrical Characteristics & AC Timing for DDR2-667 .......................................................... 16
7.4 Input AC Logic Level
...................................................................................... 16
12.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
........................................... 16
12.3 Timing Parameters by Speed Grade
.......................................................................................... 17
13.0 General notes, which may apply for all AC parameters ....................................................... 19
14.0 Specific Notes for dedicated AC parameters ........................................................................ 21
12.1 Refresh Parameters by Device Density
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Rev. 1.2 December 2008
K4T1G044QQ
K4T1G084QQ
DDR2 1.55V SDRAM
Year
2008
2008
2008
2008
- Initial Release
- typo correction
- Updated AC timing table with the JEDEC update(JESD79-2E)
- Updated AC/DC operating condition with the JEDEC update(JESD79-2E)
History
Revision History
Revision
1.0
1.01
1.1
1.2
Month
April
May
July
December
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Rev. 1.2 December 2008
K4T1G044QQ
K4T1G084QQ
1.0 Ordering Information
Org.
256Mx4
128Mx8
DDR2-667 5-5-5
K4T1G044QQ-HYE6
K4T1G084QQ-HYE6
DDR2 1.55V SDRAM
Package
60 FBGA
60 FBGA
Note :
1. Speed bin is in order of CL-tRCD-tRP.
2. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.
3. “Y” of Part number(13th digit) stands for Low Voltage product.
2.0 Key Features
Speed
CAS Latency
tRCD(min)
tRP(min)
tRC(min)
DDR2-667 5-5-5
5
15
15
60
Units
tCK
ns
ns
ns
• JEDEC Compliant V
DD
= 1.55V ± 0.05V Power Supply
• V
DDQ
= 1.55V ± 0.05V
• Backward compatible with DDR2 1.8V ± 0.1V
• 333MHz f
CK
for 667Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1, 2, 3, 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/Nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
- 50ohm ODT
- High Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than T
CASE
85°C,
3.9us at 85°C < T
CASE
< 95
°C
• All of products are Lead-Free, Halogen-Free, and RoHS
compliant
The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x
8banks, 16Mbit x 8 I/Os x 8banks device. This synchronous
device achieves high speed double-data-rate transfer rates of
667Mb/sec/pin (DDR2-667) for general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency - 1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 1Gb(x8) device receive 14/
10/3 addressing.
The 1Gb DDR2 device operates with a single 1.55V ± 0.05V
power supply and 1.55V ± 0.05V V
DDQ
.
The 1Gb DDR2 device is available in 60ball FBGAs(x4/x8).
Note : The functionality described and the timing specifications included in
his data sheet are for the DLL Enabled mode of operation.
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device
Operation & Timing Diagram”.
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Rev. 1.2 December 2008
K4T1G044QQ
K4T1G084QQ
3.0 Package Pinout/Mechanical Dimension & Addressing
DDR2 1.55V SDRAM
3.1 x4 package pinout (Top View) : 60ball FBGA Package
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
J
K
L
V
DD
NC
V
DDQ
NC
V
DDL
BA2
V
SS
V
DD
NC
V
SSQ
DQ1
V
SSQ
V
REF
CKE
BA0
A10/AP
A3
A7
A12
V
SS
DM
V
DDQ
DQ3
V
SS
WE
BA1
A1
A5
A9
NC
V
SSQ
DQS
V
DDQ
DQ2
V
SSDL
RAS
CAS
A2
A6
A11
NC
DQS
V
SSQ
DQ0
V
SSQ
CK
CK
CS
A0
A4
A8
A13
V
DDQ
NC
V
DDQ
NC
V
DD
ODT0
V
DD
V
SS
Note : V
DDL
and V
SSDL
are power and ground for the DLL. It is recommended that they be isolated on the device from V
DD
,
V
DDQ
, V
SS
, and V
SSQ
.
1
2
3
4
5
6
7
8
9
Ball Locations (x4)
A
B
C
Populated ball
Ball not populated
D
E
F
G
H
Top view
(See the balls through the package)
J
K
L
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Rev. 1.2 December 2008
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