K4T1G044QQ-HYE6T datasheet, PDF

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K4T1G044QQ-HYE6T: DescriptionDDR DRAM, 256MX4, 0.45ns, CMOS, PBGA60; Categorystorage storage; File Size832KB，42 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

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K4T1G044QQ-HYE6T Overview

DDR DRAM, 256MX4, 0.45ns, CMOS, PBGA60

K4T1G044QQ-HYE6T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SAMSUNG
package instruction	FBGA, BGA60,9X11,32
Reach Compliance Code	unknown
Maximum access time	0.45 ns
Maximum clock frequency (fCLK)	333 MHz
I/O type	COMMON
interleaved burst length	4,8
JESD-30 code	R-PBGA-B60
memory density	1073741824 bit
Memory IC Type	DDR DRAM
memory width	4
Humidity sensitivity level	3
Number of terminals	60
word count	268435456 words
character code	256000000
organize	256MX4
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA60,9X11,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH
power supply	1.55 V
Certification status	Not Qualified
refresh cycle	8192
Continuous burst length	4,8
Maximum slew rate	0.22 mA
Nominal supply voltage (Vsup)	1.55 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM

K4T1G044QQ-HYE6T Preview

K4T1G044QQ

K4T1G084QQ

DDR2 1.55V SDRAM

1Gb Q-die DDR2 1.55V SDRAM Specification

60FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.

ALL INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

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Rev. 1.2 December 2008

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K4T1G084QQ

DDR2 1.55V SDRAM

Table of Contents

1.0 Ordering Information ................................................................................................................... 4

2.0 Key Features ................................................................................................................................ 4

3.0 Package Pinout/Mechanical Dimension & Addressing ............................................................ 5

3.1 x4 package pinout (Top View) : 60ball FBGA Package

..................................................................... 5

3.2 x8 package pinout (Top View) : 60ball FBGA Package

..................................................................... 6

3.3 FBGA Package Dimension (x4/x8)

................................................................................................. 7

4.0 Input/Output Functional Description ......................................................................................... 8

5.0 DDR2 SDRAM Addressing .......................................................................................................... 9

6.0 Absolute Maximum DC Ratings ................................................................................................ 10

7.0 AC & DC Operating Conditions ................................................................................................ 10

7.1 Recommended DC Operating Conditions (SSTL - 1.8)

................................................................... 10

7.2 Operating Temperature Condition

............................................................................................... 11

7.3 Input DC Logic Level

................................................................................................................. 11

7.5 AC Input Test Conditions

........................................................................................................... 11

7.6 Differential input AC logic Level

................................................................................................. 12

7.7 Differential AC output parameters

............................................................................................... 12

8.0 ODT DC electrical characteristics ............................................................................................ 12

9.0 IDD Specification Parameters and Test Conditions ............................................................... 13

10.0 DDR2 SDRAM IDD Spec Table ................................................................................................ 15

11.0 Input/Output capacitance ........................................................................................................ 16

12.0 Electrical Characteristics & AC Timing for DDR2-667 .......................................................... 16

7.4 Input AC Logic Level

...................................................................................... 16

12.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

........................................... 16

12.3 Timing Parameters by Speed Grade

.......................................................................................... 17

13.0 General notes, which may apply for all AC parameters ....................................................... 19

14.0 Specific Notes for dedicated AC parameters ........................................................................ 21

12.1 Refresh Parameters by Device Density

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Rev. 1.2 December 2008

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K4T1G084QQ

DDR2 1.55V SDRAM

Year

2008

- Initial Release

- typo correction

- Updated AC timing table with the JEDEC update(JESD79-2E)

- Updated AC/DC operating condition with the JEDEC update(JESD79-2E)

History

Revision History

Revision

1.0

1.01

1.1

1.2

Month

April

May

July

December

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Rev. 1.2 December 2008

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K4T1G084QQ

1.0 Ordering Information

Org.

256Mx4

128Mx8

DDR2-667 5-5-5

K4T1G044QQ-HYE6

K4T1G084QQ-HYE6

DDR2 1.55V SDRAM

Package

60 FBGA

Note :

1. Speed bin is in order of CL-tRCD-tRP.

2. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.

3. “Y” of Part number(13th digit) stands for Low Voltage product.

2.0 Key Features

Speed

CAS Latency

tRCD(min)

tRP(min)

tRC(min)

DDR2-667 5-5-5

Units

tCK

• JEDEC Compliant V

= 1.55V ± 0.05V Power Supply

• V

DDQ

= 1.55V ± 0.05V

• Backward compatible with DDR2 1.8V ± 0.1V

• 333MHz f

for 667Mb/sec/pin

• 8 Banks

• Posted CAS

• Programmable CAS Latency: 3, 4, 5

• Programmable Additive Latency: 0, 1, 2, 3, 4

• Write Latency(WL) = Read Latency(RL) -1

• Burst Length: 4 , 8(Interleave/Nibble sequential)

• Programmable Sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended data-

strobe is an optional feature)

• Off-Chip Driver(OCD) Impedance Adjustment

• On Die Termination

• Special Function Support

- 50ohm ODT

- High Temperature Self-Refresh rate enable

• Average Refresh Period 7.8us at lower than T

CASE

85°C,

3.9us at 85°C < T

CASE

< 95

°C

• All of products are Lead-Free, Halogen-Free, and RoHS

compliant

The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x

8banks, 16Mbit x 8 I/Os x 8banks device. This synchronous

device achieves high speed double-data-rate transfer rates of

667Mb/sec/pin (DDR2-667) for general applications.

The chip is designed to comply with the following key DDR2

SDRAM features such as posted CAS with additive latency, write

latency = read latency - 1, Off-Chip Driver(OCD) impedance

adjustment and On Die Termination.

All of the control and address inputs are synchronized with a pair

of externally supplied differential clocks. Inputs are latched at the

crosspoint of differential clocks (CK rising and CK falling). All I/Os

are synchronized with a pair of bidirectional strobes (DQS and

DQS) in a source synchronous fashion. The address bus is used

to convey row, column, and bank address information in a RAS/

CAS multiplexing style. For example, 1Gb(x8) device receive 14/

10/3 addressing.

The 1Gb DDR2 device operates with a single 1.55V ± 0.05V

power supply and 1.55V ± 0.05V V

DDQ

The 1Gb DDR2 device is available in 60ball FBGAs(x4/x8).

Note : The functionality described and the timing specifications included in

his data sheet are for the DLL Enabled mode of operation.

Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device

Operation & Timing Diagram”.

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Rev. 1.2 December 2008

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K4T1G084QQ

3.0 Package Pinout/Mechanical Dimension & Addressing

DDR2 1.55V SDRAM

3.1 x4 package pinout (Top View) : 60ball FBGA Package

DDQ

DDL

BA2

SSQ

DQ1

SSQ

REF

CKE

BA0

A10/AP

A12

DDQ

DQ3

BA1

SSQ

DQS

DDQ

DQ2

SSDL

RAS

CAS

A11

DQS

SSQ

DQ0

SSQ

A13

DDQ

ODT0

Note : V

DDL

and V

SSDL

are power and ground for the DLL. It is recommended that they be isolated on the device from V

DDQ

, V

, and V

SSQ

Ball Locations (x4)

Populated ball

Ball not populated

Top view

(See the balls through the package)

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Rev. 1.2 December 2008

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K4T1G044QQ-HYE6T Related Products

	K4T1G044QQ-HYE6T	K4T1G084QQ-HYE60	K4T1G044QQ-HYE60	K4T1G084QQ-HYE6
Description	DDR DRAM, 256MX4, 0.45ns, CMOS, PBGA60	DDR DRAM, 128MX8, 0.45ns, CMOS, PBGA60, HALOGEN FREE AND ROHS COMPLIANT, FBGA-60	DDR DRAM, 256MX4, 0.45ns, CMOS, PBGA60, HALOGEN FREE AND ROHS COMPLIANT, FBGA-60	DDR DRAM, 128MX8, 0.45ns, CMOS, PBGA60
Is it Rohs certified?	conform to	conform to	conform to	conform to
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Reach Compliance Code	unknown	unknown	unknown	unknown
Maximum access time	0.45 ns	0.45 ns	0.45 ns	0.45 ns
Maximum clock frequency (fCLK)	333 MHz	333 MHz	333 MHz	333 MHz
I/O type	COMMON	COMMON	COMMON	COMMON
interleaved burst length	4,8	4,8	4,8	4,8
JESD-30 code	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60
memory density	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	4	8	4	8
Humidity sensitivity level	3	3	3	3
Number of terminals	60	60	60	60
word count	268435456 words	134217728 words	268435456 words	134217728 words
character code	256000000	128000000	256000000	128000000
organize	256MX4	128MX8	256MX4	128MX8
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FBGA	TFBGA	TFBGA	FBGA
Encapsulate equivalent code	BGA60,9X11,32	BGA60,9X11,32	BGA60,9X11,32	BGA60,9X11,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, FINE PITCH
power supply	1.55 V	1.55 V	1.55 V	1.55 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192
Continuous burst length	4,8	4,8	4,8	4,8
Maximum slew rate	0.22 mA	0.225 mA	0.22 mA	0.225 mA
Nominal supply voltage (Vsup)	1.55 V	1.55 V	1.55 V	1.55 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
package instruction	FBGA, BGA60,9X11,32	TFBGA, BGA60,9X11,32	TFBGA, BGA60,9X11,32	-

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