F71889A
F71889A
Super Hardware Monitor + LPC I/O
Release Date: Sep, 2011
Version: V0.21P
Sep, 2011
V0.21P
F71889A
F71889A Datasheet Revision History
Version
V0.10P
V0.11P
~
V0.19P
V0.20P
Date
2010/4
2010/5
~
2011/6
2011/7/18
72-73
Add USBEN/VCCGATE timing and SUSC# timing
Protection Mode Configuration Register
⎯
Index 02h, bit 3
Page
-
Preliminary Version.
Revision History
-
Shorten history description
V0.21P
2011/9/14
Made Correction & Clarification
Update VIN3 (pin96) description
Please note that all data and specifications are subject to change without notice. All the trade marks of products
and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for use
in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such
improper use or sales.
Sep, 2011
V0.21P
F71889A
Table of Content
General Description ........................................................................................................ 1
Feature List ..................................................................................................................... 1
Key Specification ............................................................................................................ 4
Block Diagram ................................................................................................................ 5
Pin Configuration ............................................................................................................ 6
Pin Description ............................................................................................................... 7
6.1 Power Pin .................................................................................................................... 7
6.2 LPC Interface .............................................................................................................. 8
6.3 UART, GPIO and 80-Port ............................................................................................ 8
6.4 Parallel Port .............................................................................................................. 10
6.5 Hardware Monitor, SIR, CIR, ERP ............................................................................ 11
6.6 KBC Function ............................................................................................................ 13
6.7 CIR, GPIO, Others Function ..................................................................................... 13
6.8 ACPI Function Pins ................................................................................................... 14
7.
Function Description ..................................................................................................... 16
7.1. Power on Strapping Option ....................................................................................... 16
7.2. Hardware Monitor...................................................................................................... 16
7.3. Hardware Monitor Register ....................................................................................... 30
7.4. Keyboard Controller .................................................................................................. 63
7.5. 80 Port ...................................................................................................................... 65
7.6. ACPI Function ........................................................................................................... 65
7.7. PECI Function ........................................................................................................... 71
7.8. SST Function ............................................................................................................ 72
7.9. TSI Function .............................................................................................................. 72
7.10. Power Saving Function ......................................................................................... 72
7.11. CIR Function ......................................................................................................... 74
7.12. Scan Code Function ............................................................................................. 75
8
Register Description ..................................................................................................... 76
8.1 Global Control Registers ........................................................................................... 80
8.2 UART1 Registers (CR01) .......................................................................................... 85
8.3 UART 2 Registers (CR02) ......................................................................................... 86
8.4 Parallel Port Registers (CR03) .................................................................................. 87
8.5 Hardware Monitor Registers (CR04) ......................................................................... 88
8.6 KBC Registers (CR05) .............................................................................................. 88
1.
2.
3.
4.
5.
6.
Sep, 2011
V0.21P
F71889A
8.7 GPIO Registers (CR06) (All registers of GPIO are powered by VSB3V) .................. 89
8.8 Watch Dog Timer Registers (CR07) ........................................................................ 104
8.9 CIR Registers (CR08) ............................................................................................. 105
8.10 PME, ACPI and ERP Registers (CR0A) .................................................................. 106
8.11 VREF Control Registers (CR0B) ............................................................................. 114
Electrical Characteristics ............................................................................................ 115
Ordering Information ................................................................................................... 118
Top Marking Specification ........................................................................................... 118
Package Dimensions .................................................................................................. 119
Application Circuit ....................................................................................................... 120
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Sep, 2011
V0.21P
F71889A
1. General Description
The F71889A which is the featured IO chip for new generational PC system is equipped
with one IEEE 1284 parallel port, two UART ports, KBC, 80-Port (multi with COM2), CIR with
RC6 and SMK QP protocols supported and 54 GPIO pins. The F71889A integrated with
hardware monitor, 9 sets of voltage sensor, 3 sets of creative auto-controlling fans and 3
temperature sensor pins for the accurate dual current type temp. measurement for CPU
thermal diode or external transistors 2N3906.
The F71889A provides flexible features for multi-directional application. For instance,
IRQ sharing function also designed in UART feature for particular usage and accurate current
mode H/W monitor will be worth in measurement of temperature, provides 3 modes fan speed
control mechanism included Manual Mode/Speed Mode/Temperature Mode for users’
selection.
Additionally, integrated 80-Port, and 5VDUAL voltage switch and adjustable voltage
reference outputs related functions. The 80-Port is for engineering and debuging usage.
F71889A also provides 5V dual controller and some voltage reference outputs for system
application. Others, the F71889A supports newest AMD new interface TSI and Intel PECI 3.0
/SST interfaces and INTEL IBX PEAK SMBus for temperature reading. These features will
help you more and improve product value.
In order to save the current consumption when the system is in the soft off state which is
so called power saving function. The power saving function supports the system boot-on not
only by pressing the power button but also by the wake-up events (GPIO5x, CIR, RI#) . When
the system enters the S3/S4/S5 state, F71889A can cut off the VSB power rail which supplies
power source to the devices like the LAN chip, the chipset, the SIO, the audio codec, DRAM,
and etc. The PC system can be simulated to G3-like state when the system enters S3/S4/S5
states. At the G3-like state, the F71889A consumes 5VSB power rail only. The integrated two
control pins are utilized to turn on or off VSB power rail in the G3-like status. The turned on
VSB rail is supplied to a wake up device to fulfill a low power consumption system which
supports a wake up function.
Finally, the F71889A is powered by 3.3V voltage, with the LPC interface in the package
of 128-LQFP (14mm*14mm) green package.
2. Feature List
General Functions
Comply with LPC Spec. 1.1
Support DPM (Device Power Management), ACPI
Provides two UARTs, KBC and Parallel Port
-1-
Sep, 2011
V0.21P
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