DATA SHEET
4GB DDR3 SDRAM SO-DIMM
EBJ40UG8BBU0 (512M words
×
64 bits, 1 Rank)
Specifications
•
Density: 4GB
•
Organization
512M words
×
64 bits, 1 rank
•
Mounting 8 pieces of 4G bits DDR3 SDRAM sealed
in FBGA
•
Package: 204-pin socket type small outline dual
in-line memory module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant) and Halogen-free
•
Power supply: VDD
=
1.5V
±
0.075V
•
Data rate: 1600Mbps/1333Mbps (max.)
Backward compatible to1066Mbps/800Mbps/667Mbps
•
Eight internal banks for concurrent operation
(components)
•
Interface: SSTL_15
•
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
•
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
•
/CAS write latency (CWL): 5, 6, 7, 8
•
Precharge: auto precharge option for each burst
access
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
Operating case temperature range
TC = 0°C to +95°C
Features
•
Double-data-rate architecture: two data transfers per
clock cycle
•
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
•
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
•
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Posted /CAS by programmable additive latency for
better command and data bus efficiency
•
On-Die-Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
•
Multi Purpose Register (MPR) for pre-defined pattern
read out
•
ZQ calibration for DQ drive and ODT
•
Programmable Partial Array Self-Refresh (PASR)
•
/RESET pin for Power-up sequence and reset
function
•
SRT range:
Normal/extended
•
Programmable Output driver impedance control
Document No. E1833E20 (Ver. 2.0)
Date Published September 2011 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2011
EBJ40UG8BBU0
Ordering Information
Data rate
Mbps (max.)
1600
1333
Component
JEDEC speed bin
(CL-tRCD-tRP)
Contact
pad
Part number
EBJ40UG8BBU0-GN-F
EBJ40UG8BBU0-DJ-F
Package
Mounted devices
EDJ4208BBBG-GN-F
EDJ4208BBBG-GN-F
EDJ4208BBBG-DJ-F
DDR3-1600K (11-11-11) 204-pin SO-DIMM
(lead-free and
Gold
DDR3-1333H (9-9-9)
halogen-free)
Detailed Information
For detailed electrical specifications and further information, please refer to the component DDR3 SDRAM datasheet
EDJ4204BBBG, EDJ4208BBBG (E1800E).
Data Sheet E1833E20 (Ver. 2.0)
2
EBJ40UG8BBU0
Pin Configurations
Front side
Pin
No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
Pin name
VREFDQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
/DQS1
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
/DQS2
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
Back side
Pin
No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
Pin name
VSS
DQ4
DQ5
VSS
/DQS0
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
/RESET
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
/DQS3
DQS3
VSS
DQ30
DQ31
VSS
Front side
Pin
No.
Pin name
Back side
Pin
No.
KEY
Pin name
Front side
Pin
No.
143
Pin name
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
/DQS6
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
Back side
Pin
No.
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
Pin name
VSS
DQ44
DQ45
VSS
/DQS5
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
/DQS7
DQS7
VSS
DQ62
DQ63
VSS
NC
SDA
SCL
VTT
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
CKE0
VDD
NC
BA2
VDD
A12(/BC)
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
/CK0
VDD
A10(AP)
BA0
VDD
/WE
/CAS
VDD
A13
NC
VDD
NC
VSS
DQ32
DQ33
VSS
/DQS4
DQS4
VSS
DQ34
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
NC
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
/CK1
VDD
BA1
/RAS
VDD
/CS0
ODT0
VDD
NC
NC
VDD
VREFCA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
Data Sheet E1833E20 (Ver. 2.0)
3
EBJ40UG8BBU0
Pin Description
Pin name
A0 to A15
A10 (AP)
A12 (/BC)
BA0, BA1, BA2
/RAS
/CAS
/WE
/CS0
CKE0
CK0, CK1
/CK0, /CK1
ODT0
DQ0 to DQ63
DQS0 to DQS7, /DQS0 to /DQS7
DM0 to DM7
SCL
SDA
SA0, SA1
VDD*
1
Function
Address input
Row address
Column address
Auto precharge
Burst chop
Bank select address
Row address strobe
Column address strobe
Write enable
Chip select
Clock enable
Clock input
Differential clock input
ODT control
Data input/output
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Address input for serial PD
Power for internal circuit
Power for serial PD
Reference voltage for CA
Reference voltage for DQ
Ground
I/O termination supply for SDRAM
Set DRAM to a known state
No connection
A0 to A15
A0 to A9
VDDSPD
VREFCA
VREFDQ
VSS
VTT
/RESET
NC
Note: 1. The VDD and VDDQ pins are tied common to a single power-plane on these designs.
Front side
1 pin
71 pin 73 pin
203 pin
2 pin
72 pin 74 pin
204 pin
Back side
Data Sheet E1833E20 (Ver. 2.0)
4
EBJ40UG8BBU0
Serial PD Matrix
-DJ
Byte No. Function described
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Number of serial PD bytes written/
SPD device size/CRC coverage
SPD revision
Key byte/DRAM device type
Key byte/module type
SDRAM density and banks
SDRAM addressing
Module nominal voltage, VDD
Module organization
Module memory bus width
Fine timebase (FTB) dividend/divisor
Medium timebase (MTB) dividend
Medium timebase (MTB) divisor
SDRAM minimum cycle time (tCK (min.))
Reserved
SDRAM CAS latencies supported, LSB
SDRAM CAS latencies supported, MSB
SDRAM minimum CAS latencies time (tAA (min.))
SDRAM minimum write recovery time (tWR (min.))
Hex
92h
10h
0Bh
03h
04h
21h
00h
01h
03h
52h
01h
08h
0Ch
00h
7Eh
00h
69h
78h
Comments
176/256/0-116
Rev.1.0
DDR3 SDRAM
SO-DIMM
4G bits, 8 banks
16 rows, 10 columns
1.5V
1 rank/×8 bits
64 bits/non-ECC
5/2
1
8
1.5ns
—
5, 6, 7, 8, 9, 10
—
13.125ns
15ns
13.125ns
6ns
13.125ns
—
36ns
49.125ns
260ns
260ns
7.5ns
7.5ns
30ns
30ns
DLL-off, RZQ/6, 7
PASR/2X refresh at
+85ºC to +95ºC
Not incorporated
Standard
-GN
Hex
92h
10h
0Bh
03h
04h
21h
00h
01h
03h
52h
01h
08h
0Ah
00h
FEh
00h
69h
78h
69h
30h
69h
11h
18h
81h
20h
08h
3Ch
3Ch
00h
F0h
83h
81h
00h
00h
Comments
176/256/0-116
Rev.1.0
DDR3 SDRAM
SO-DIMM
4G bits, 8 banks
16 rows, 10 columns
1.5V
1 rank/×8 bits
64 bits/non-ECC
5/2
1
8
1.25ns
—
5, 6, 7, 8, 9, 10, 11
—
13.125ns
15ns
13.125ns
6ns
13.125ns
—
35ns
48.125ns
260ns
260ns
7.5ns
7.5ns
30ns
30ns
DLL-off, RZQ/6, 7
PASR/2X refresh at
+85ºC to +95ºC
Not incorporated
Standard
SDRAM minimum /RAS to /CAS delay (tRCD (min.)) 69h
SDRAM minimum row active to row active delay
(tRRD (min.))
SDRAM minimum row precharge time (tRP (min.))
SDRAM upper nibbles for tRAS and tRC
SDRAM minimum active to precharge time
(tRAS (min.)), LSB
30h
69h
11h
20h
SDRAM minimum active to active /auto-refresh time
89h
(tRC (min.)), LSB
SDRAM minimum refresh recovery time delay
(tRFC (min.)), LSB
SDRAM minimum refresh recovery time delay
(tRFC (min.)), MSB
SDRAM minimum internal write to read
command delay (tWTR (min.))
SDRAM minimum internal read to precharge
command delay (tRTP (min.))
Upper nibble for tFAW
Minimum four activate window delay time
(tFAW (min.))
SDRAM optional features
SDRAM thermal and refresh options
Module thermal sensor
SDRAM device type
20h
08h
3Ch
3Ch
00h
F0h
83h
81h
00h
00h
Data Sheet E1833E20 (Ver. 2.0)
5
ARM Technology
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