ELM743xxA
CMOS Low power voltage dual comparator
■General description
Preliminary
ELM743xxA is a low voltage and low power dual comparator which can input and output signals in full range
of Vdd to Vss. ELM743xxA can operate with single power source and low voltage supply (operating voltage
range:Vdd≥1.2V) condition. ELM743xxA provides 2 kinds of output style: N-ch opendrain and CMOS output.
■Features
• Low voltage operation
: Vdd≥1.2V
• Low current consumption : Typ.2μA(Vdd=3.6V, VoutA=VoutB=Low)
Typ.1.2μA(Vdd=3.6V, VoutA=VoutB=High)
• Operating voltage range : 1.2V≤Vdd≤7.0V
• Input voltage range
: Vss to Vdd
• Output stage
: N-ch open drain or CMOS output selectable
• Package
: TSON8-2×2, MSOP-8
■Application
• Battery-operated devices
• Micropower signal processing
• Low voltage analog circuits
■Maximum absolute ratings
Parameter
Power supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Symbol
Vdd
Vin
Vout
Pd
Top
Tstg
Limit
Vss-0.3 to +8.0
Vss-0.3 to Vdd+0.3
N-ch : Vss-0.3 to +8.0
CMOS : Vss-0.3 to Vdd+0.3
200 (TSON8-2×2)
250 (MSOP-8)
-20 to +70
-55 to +125
Unit
V
V
V
mW
°C
°C
■Selection guide
ELM743xxA-x
Symbol
a
b
c
d
Output form
Package
Product version
Taping direction
N : N-ch open drain
C : CMOS
M : TSON8-2×2
N : MSOP-8
C(fixed)
S: Refer to PKG file
N: Refer to PKG file
ELM743 x x A - x
↑ ↑↑ ↑
a b c d
4- 1
Rev.1.0
ELM743xxA
CMOS Low power voltage dual comparator
■Pin configuration
TSON8-2×2(TOP VIEW)
1
2
3
4
A
- +
Preliminary
MSOP-8(TOP VIEW)
1
2
3
4
A
-
+
8
7
+
B
-
8
7
B
+
-
6
5
6
5
Pin No.
1
2
3
4
5
6
7
8
Pin name
OUTA
IN-A
IN+A
VSS
IN+B
IN-B
OUTB
VDD
■Electrical characteristics
Parameter
Power supply voltage
Common-mode input voltage
Input offset voltage
Input current
Output current
Current consumption
Response time
Symbol
Vdd
Vicr
Vio-1
Vio-2
Iin
IoutN-1
IoutN-2
IoutP-1
IoutP-2
Iss-1
Iss-2
tHL
tLH
Condition
Vdd=1.2 to 7.0V
Vicr=Vss to Vdd-1V
Vicr=Vdd-1V to Vdd
Vdd=1.2 to 7.0V
Vdd=1.2V, Vout=0.4V
Vdd=1.5V, Vout=0.4V
Vdd=1.2V, Vout=0.6V
Vdd=1.5V, Vout=1.1V
Vdd=3.6V, Vout:"L"
Vdd=7.0V, Vout:"L"
Vdd=3.6V
Vdd=3.6V
Min.
1.2
Vss
1.8
4.0
0.15
0.35
Vss=0V, Top=25°C
Typ.
Max.
Unit
7.0
V
Vdd
V
8
mV
12
mV
100
pA
4.0
mA
6.0
0.30
mA
0.45
2.0
5.6
μA
2.2
6.0
μA
30
μs
30
μs
■Marking
TSON8-2×2
MSOP-8
7 4 3a
bcd
7 4 3a
bcd
Symbol
a
b, c, d
Mark
N : N-ch open drain
C : CMOS
000 to 999
Content
Output stage
Assembly Lot No.
4- 2
Rev.1.0
ELM743xxA
CMOS Low power voltage dual comparator
■Typical operating characteristics
Iss-Vdd
3.0
Preliminary
Offset voltage distribution (Vicr=Vss)
VOS - Distribution
25
Vdd=3.6V, Vicr=0V
Iss - Vdd
Top=70
½
, Vout="L"
Top=25
½
, Vout="L"
Top=-20
½
, Vout="L"
2.5
20
Percent (%)
Iss (½½½
2.0
15
1.5
1.0
0.5
Top=70
½
, Vout="H"
Top=25
½
, Vout="H"
Top=-20
½
, Vout="H"
10
5
0
1
2
Vdd (V)
3
4
5
6
7
-8
-6
-4
-2
VOS (mV)
0
2
4
6
8
Offset voltage distribution (Vicr=Vdd/2)
VOS - Distribution
25
20
Vdd=3.6V, Vivr=1.8V
Offset voltage distribution (Vicr=Vdd)
VOS - Distribution
12
10
Vdd=3.6V, Vicr=3.6V
Percent (%)
15
10
Percent (%)
8
6
4
5
2
-6
-8
-4
-2
VOS (mV)
0
2
4
6
8
-10
-8
-6
-4
-2
VOS (mV)
0
2
4
6
8
10
IoutN - Vdd
40
Vout=0.4V
IoutP - Vdd
2.5
Vout=Vdd-0.4V
30
2.0
IoutN (mA)
IoutP (mA)
1.5
20
4-3
Rev.1.0
1.0
10
0.5
Per
Per
10
10
5
5
4
4
2
2
-8
-8
ELM743xxA
CMOS
8
power voltage dual comparator
6
Low
-10
-8
-6
-4
-2
0
2
4
2
4
-6
-4
-2
0
6
-6
-4
-2
0
(mV)
2
VOS
VOS (mV)
4
6
8
-2
(mV)
-10
-8
-6
-4
VOS
0
2
4
VOS (mV)
6
8
10
8
10
Preliminary
IoutN-Vdd (Vout=0.4V)
40
40
30
30
20
20
10
10
IoutN - Vdd
IoutN - Vdd
IoutP-Vdd (Vout=Vdd to 0.4V)
2.5
2.5
Vout=0.4V
Vout=0.4V
IoutP - Vdd
IoutP - Vdd
Vout=Vdd-0.4V
Vout=Vdd-0.4V
2.0
2.0
IoutN (mA)
IoutN (mA)
IoutP (mA)
IoutP (mA)
0
0
1
1
2
2
3
4
3
(V)
4
Vdd
1.5
1.5
1.0
1.0
0.5
0.5
5
5
6
6
7
7
Vdd (V)
0
0
1
1
2
2
4
3
4
3
(V)
Vdd
Vdd (V)
5
5
6
6
7
7
tHL, tLH-Vdd
80
80
70
70
60
60
50
50
40
40
30
30
20
20
10
10
Vin+=Vdd/2, Vin-=Vdd / to
-
0.05V
½
Vdd /2+0.05V
tHL, tLH Vdd
Vin+=Vdd/2, Vin-=Vdd / to 0.05V
½
Vdd /2+0.05V
tHL, tLH-Top (Vdd=3.6V)
30
30
Vdd=3.6V, Vin+=1.8V,
Top
tHL, tLH -
Vin-=1.75
½
1.85V
Vdd=3.6V, Vin+=1.8V, Vin-=1.75
½
1.85V
tHL, tLH - Vdd
tHL, tLH - Top
25
25
tHL, tLH (½s)
tHL, tLH (½s)
tHL, tLH (½s)
tHL, tLH (½s)
tHL
tHL
20
20
tHL
tHL
15
15
tLH
tLH
10
10
tLH
tLH
5
5
0
0
1
1
2
2
3
4
3
4
Vdd (V)
Vdd (V)
5
5
6
6
7
7
-20
-10
0
-20
-10
0
10
20
30
40
50
60
70
10
Top (½)
40
50
60
70
20
30
Top (½)
4- 4
Rev.1.0
FPGA/CPLD
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